SOI device structure and manufacturing method thereof

Abstract

The invention provides an SOI device structure and a manufacturing method thereof. The manufacturing method comprises steps of forming an insulator upper silicon structure; forming a device active region of the first doping type which is separated and surrounded by shallow trenches in a silicon top layer; forming a grid structure on the top of the device active region; forming a groove adjacently with a drain region through the lithography and etching technology by use of a light cover; then, forming grid side walls on the two sides of the grid structure through the self-alignment technology and forming groove side walls on the two sides of the groove; forming a source region of the second coping type and the drain region on the surface of the device active region in a self-alignment manner on the two sides of the grid structure; forming a contact region of the first doping type under the groove; forming contact layers on the exposed surface of the contact region, the exposed surface of the source region and the exposed surface of the drain region; forming a covering layer on the silicon top layer; and forming through holes for being respectively connected to the exposed surface of the contact region, the exposed surface of the source region and the exposed surface of the drain region in the covering layer.

Description

technical field [0001] The invention relates to the fields of semiconductor design and semiconductor manufacturing; more specifically, the invention relates to an SOI device structure, and the invention also relates to a corresponding SOI device structure manufacturing method. Background technique [0002] Silicon is the most widely used primary raw material in the semiconductor industry, and most chips are made of silicon wafers. Silicon-on-insulator (SOI, Silicon-on-insulator) is a special silicon chip, the main feature of its structure is to insert an insulating layer (buried oxide layer) between the active layer and the substrate layer to isolate the active layer and The electrical connection between substrates, this structural feature brings many advantages such as small parasitic effects, fast speed, low power consumption, high integration, and strong radiation resistance to silicon-on-insulator devices. [0003] figure 1 A silicon-on-insulator structure is schematic...

AI Technical Summary

Problems solved by technology

However, this VSTI technology results in a relatively large overall device structure area, which is not conducive to the miniaturization of electronic products

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