Split-phase clock TDC based on ISERDES series chain and measurement method

Abstract

The invention relates to the field of time measurement, in particular to a split-phase clock TDC based on an ISERDES tandem chain and a measurement method. ISERDES cores in a plurality of FPGAs are connected in series through technical means to achieve multiple measurements of input signals and improve the time measurement precision, the TDC is subjected to performance test in a K7 FPGA, and the result shows that the time measurement precision is better than 40 ps RMS. The dead time is less than 20 ns.

Description

technical field [0001] The invention relates to the field of time measurement, in particular to a phase-splitting clock TDC based on an ISERDES serial chain and a measurement method. Background technique [0002] In some scientific or commercial instruments, such as nuclear medicine imaging equipment, high-precision time measurements are required. At present, high-precision time measurement can be completed based on Application Specific Integrated Circuit (ASIC), which is widely used due to its advantages of high precision and strong stability. However, ASIC also has disadvantages such as high cost and long development cycle. [0003] In recent years, time-digital converters (TDC) based on programmable logic gate arrays (Field Programmable Gate Array, FPGA) have been widely valued for their high integration, low cost, flexible configuration and high precision. Various types of FPGA-TDCs have been developed, such as TDCs based on the carry chain structure and the principle ...

AI Technical Summary

Problems solved by technology

The FPGA-TDC based on the carry chain structure uses the internal carry chain resources of the FPGA to mark the arrival time of the signal to be measured by inputting the different level states of the signal to be measured on each tap of the carry chain. This type of TDC has the advantage of high precision. However, due to the different delay values ​​of the delay units of different types of devices, the defect of poor portability is caused

The FPGA-TDC based on the principle of clock phase separation uses high-frequency clocks with different phases to latch the signal to be tested, and marks the arrival time of the signal to be tested through the different latch states of each clock. This type of TDC has a simple structure and can The advantage of strong portability, but its measurement accuracy is limited by the clock frequency and phase, only to the order of hundreds of picoseconds

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