Fin field effect transistor and layout structure thereof

Abstract

The invention provides a fin field effect transistor and a layout structure thereof. The fin field effect transistor comprises a substrate; a fin structure on the substrate; a grid electrode, a sourceelectrode and a drain electrode which are located on the substrate and cover part of the fin-type structure, wherein the source electrode is electrically connected with the source electrode area on the fin-type structure, and the drain electrode is electrically connected with the drain electrode area on the fin-type structure; a first leading-out wire which is located on the source electrode andelectrically connected with the source electrode, and a second leading-out wire which is located on the first leading-out wire and electrically connected with the first leading-out wire, wherein the distance between the boundary of the first leading-out wire and the boundary of the second leading-out wire adjacent to the first leading-out wire is greater than a preset distance; a third leading-outwire which is located on the drain electrode and electrically connected with the drain electrode, and a fourth leading-out wire which is located on the third leading-out wire and electrically connected with the third leading-out wire, wherein the distance between the boundary of the third leading-out wire and the boundary of the adjacent fourth leading-out wire is greater than the preset distance, so the selection difficulty of the leading-out wires can be reduced, and the layout design efficiency of the fin field effect transistor is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, more specifically, to a fin field effect transistor and its layout structure. Background technique [0002] The source and drain of a traditional Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) are electrically connected to an external circuit through an external lead wire. However, for a new type of Fin Field-Effect Transistor (FINFET), since its source and drain have a three-dimensional structure connected thereto, the three-dimensional structure includes a local interconnection layer and a contact hole, therefore, In addition to the external connection through the external lead-out line, the external connection can also be made through the internal lead-out line of the local interconnection layer. [0003] However, if the parameterizable unit is designed according to the minimum design rules, such as figure 1 As shown, the boundary distance D between the extern...

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Problems solved by technology

[0003] However, if the parameterizable unit is designed according to the minimum design rules, such as figure 1 As shown, the boundary distance D between the external lead-out line 10 and the internal lead-out line 11 will be very close to the minimum layout length unit of 1 nanometer, even if the layout engineer maximizes the magnification, but because the selectable area of ​​the internal lead-out line 11 is very small, Therefore, it is still difficult to click to the internal pinout 11, causing the layout engineer to spend more time on the selected layer

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