SOI device capable of reducing alignment difficulty and preparation method thereof

Abstract

The invention provides an SOI device capable of reducing alignment difficulty and a preparation method thereof. The preparation method comprises the steps that an SOI composite substrate is prepared,the SOI composite substrate comprises a bottom semiconductor layer, an insulating layer and a top semiconductor layer from bottom to top, a plurality of cavities distributed at intervals are formed inthe insulating layer, and the top semiconductor layer covers the cavities; an alignment mark is formed on the insulating layer and / or in the bottom semiconductor layer; the top semiconductor layer isetched to define a preparation region of the active region; a gate dielectric material layer and a gate material layer are formed and etched to form a gate structure; ion implantation is performed onthe active region to form a source region and a drain region; and a source electrode and a drain electrode are respectively prepared in the source region and the drain region, and the overlapping region of the cavity and the gate structure is greater than 1 / 2 of the thickness of the top semiconductor layer. The alignment mark is prepared in the preparation process of the SOI composite substrate,the grid alignment difficulty can be remarkably reduced by presetting the multi-cavity structure, and the tape-out yield of devices and circuits can be improved.

Description

technical field [0001] The invention belongs to the field of design and manufacture of semiconductor devices, in particular to an SOI device capable of reducing alignment difficulty and a preparation method thereof. Background technique [0002] SOI composite substrates with cavities are increasingly used in power devices. This is because the cavity can play the role of insulation, etc., and semiconductor functional devices are prepared on the cavity, so that the good sub-threshold characteristics of the device can be maintained. In addition, with the increasing integration of devices and the shrinking of device volume, power consumption and leakage current have become issues that need to be focused on. Therefore, the silicon-on-insulator (SOI) structure can well suppress short-channel effect and the ability to improve device scaling has become the preferred structure for deep submicron MOS devices. For SOI MOSFET devices with embedded cavities, because the cavity structur...

AI Technical Summary

Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an SOI device and its preparation method that can reduce the difficulty of alignment, which is used to solve the problem in the prior art that the reduction of the characteristic size of the cavity is limited. In the subsequent tape-out process, it is necessary to align the gate with the cavity so that more than half of the gate structure falls above the cavity. Since the cavity is buried under the top silicon, it is difficult to ensure alignment accuracy, especially in the first When aligning, it is difficult to align, and the existing devices have poor radiation resistance and other problems

Images