A high-speed parallel decoding method for regular sparse code division multiple access scma based on gpu
A sparse code division multiple access and decoding technology, which is applied in the field of communication, can solve the problems of high complexity of SCMA decoding, and achieve the effects of optimization efficiency, high calculation efficiency, and reduced startup overhead
Active Publication Date: 2022-08-05
HANGZHOU INNOVATION RES INST OF BEIJING UNIV OF AERONAUTICS & ASTRONAUTICS
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[0004] The purpose of the present invention is to provide a GPU-based regular sparse code division multiple access SCMA high-speed parallel decoding method to solve the problem of high complexity of SCMA decoding in the prior art, and to use the parallel core resources of the GPU to improve computing efficiency
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[0027] The present invention will be described in detail below with reference to the accompanying drawings.
[0028] The present invention provides a GPU-based regular sparse code division multiple access (SCMA) high-speed parallel decoding method, which adopts a method based on a factor graph (such as figure 1 shown) iterative decoding algorithm in logarithmic domain. The decoding method includes three stages: initialization stage, decoding and decision stage, and result return stage. The initialization stage includes the following steps 1 and 2, the decoding and decision stage includes the following steps 3 to 5, and the following step 6 is the result return stage. The entire decoding process is as follows: figure 2 shown, as follows:
[0029] Step 1: Host initialization. Including allocating memory space for codebook information, codebook factor graph information, signal received by receiver, channel state information, the result of decoding decision, i.e. log-likelihoo...
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The invention discloses a GPU-based regular SCMA high-speed parallel decoding method. The decoding process can be divided into three stages: an initialization stage, a decoding and judgment stage, and a result return stage; the initialization stage includes the following steps 1 And step 2, the decoding and decision stage includes the following steps 3 to 5, and the following step 6 is the result return stage; the decoding method of the present invention includes two levels of parallelism. The first level is parallelism between thread blocks. There is a one-to-one correspondence between thread blocks and data blocks, and each thread block can run independently and in parallel. The second level is parallelism between threads within a thread block. The method of the invention has high calculation efficiency and low synchronization overhead. The GPU memory allocation method used in the present invention achieves an optimal balance between the efficiency of accessing the memory and the space requirement according to the characteristics of the global memory and the shared memory in terms of access speed and capacity, and the locality of the access is good, and the memory access and memory are optimized. storage efficiency.
Description
technical field [0001] The invention belongs to the technical field of communication, and relates to a regular sparse code division multiple access SCMA high-speed parallel decoding method based on a GPU (Graphics Processing Unit, graphics processor). Background technique [0002] In order to realize the "Internet of Everything", the future wireless communication system needs to support the connection of massive terminals. For this reason, various non-orthogonal multiple access technologies, especially Sparse Code Multiple Access (SCMA, Sparse Code Multiple Access), have attracted much attention from academia and industry. SCMA includes regular SCMA and non-regular SCMA. Regular SCMA has a simple structure and can provide more than three times the number of connections compared with orthogonal multiple access. Organizations submit proposals to rule SCMA. However, the decoding complexity of SCMA (including regular SCMA and irregular SCMA) is very high, even if the approxima...
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IPC IPC(8): G06F9/38G06F9/50G06F9/54H04L1/00H03M13/29
CPCG06F9/38G06F9/5016G06F9/544H04L1/005H03M13/2948
Inventor 李舒韩玉玺
Owner HANGZHOU INNOVATION RES INST OF BEIJING UNIV OF AERONAUTICS & ASTRONAUTICS