Method for obtaining on-resistance of wafer edge

Abstract

The invention discloses a method for obtaining on-resistance of a wafer edge, and relates to the field of semiconductor manufacturing. The method comprises the steps: establishing a fitting function model of an on-resistance drift value and an offset distance by utilizing a plurality of sample wafers, wherein the offset distance is the distance between the edge of the wafer and a preset position in a central area of a measurement clamp; obtaining the on-resistance of the edge of the wafer to be tested, and recording the on-resistance as the initial on-resistance; obtaining an offset distance corresponding to the edge of the wafer to be tested; substituting the offset distance corresponding to the edge of the to-be-tested wafer into the fitting function model to obtain an on-resistance drift value of the to-be-tested wafer; and obtaining a conduction resistance correction value of the edge of the wafer to be tested according to the initial conduction resistance and the conduction resistance drift value; the problem that at present, due to the characteristics of a measuring clamp, the measured on-resistance of the edge of a wafer is likely to be too large is solved. The effects of correcting the on-resistance of the edge of the wafer, reducing the test error and improving the stability and accuracy of the test data are achieved.

Description

technical field [0001] The present application relates to the field of semiconductor manufacturing, in particular to a method for obtaining the on-resistance of a wafer edge. Background technique [0002] The on-resistance is the drain-source distance when the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor) is turned on under the condition of specific gate-source voltage (Vgs) and drain terminal current (Id). the maximum impedance. The on-resistance determines the power dissipated when the MOSFET is turned on. [0003] After the chips on the wafer are fabricated, on-resistance testing is performed at the wafer level. During testing, the back of the wafer to be tested is connected to the probe station, and the chip on the front of the wafer is connected to the probes in the probe card. During the test of on-resistance, the resistance value of on-resistance is affected by many factors, and on-resistance R dson I...

AI Technical Summary

Problems solved by technology

[0006] Due to the characteristics of the fixture itself, such as uneven negative pressure distribution, surface flatness, etc., the contact resistance R between the edge of the fixture and the wafer cedge Greater than the contact resistance R between the center of the fixture and the wafer ccenter , resulting in the measured on-resistance of the wafer edge being greater than that of other regions of the wafer, reducing the accuracy of the test data

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