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Multi-chip 3D stacked packaging structure with efficient heat dissipation and packaging method

A packaging structure and packaging method technology, applied in electrical components, electrical solid devices, circuits, etc., can solve problems affecting chip performance, and achieve the effect of improving reliability

Active Publication Date: 2020-12-15
广东佛智芯微电子技术研究有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the embodiment of the present application is to provide a multi-chip 3D stacked packaging structure and packaging method with high heat dissipation, to solve the problems caused by components with high heat consumption volume and density such as power devices in the existing multi-chip stacked packaging structure A large amount of heat will be transferred to other chips vertically and horizontally, affecting the performance of other chips, which can improve the heat dissipation effect of the multi-chip stacked package structure

Method used

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  • Multi-chip 3D stacked packaging structure with efficient heat dissipation and packaging method
  • Multi-chip 3D stacked packaging structure with efficient heat dissipation and packaging method
  • Multi-chip 3D stacked packaging structure with efficient heat dissipation and packaging method

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Embodiment 1

[0049] Please also refer to figure 1 , figure 1It is a structural schematic diagram of an efficient heat dissipation multi-chip 3D stack package structure according to Embodiment 1 of the present application. The highly efficient heat dissipation multi-chip 3D stack package structure includes:

[0050] redistribution layer 10;

[0051] The first chip 20, the first chip 20 is disposed on the redistribution layer 10, and is electrically connected to the redistribution layer 10;

[0052] A power device 30, the power device 30 is also disposed on the redistribution layer 10, and is electrically connected to the redistribution layer 10;

[0053] The first heat insulation element 40, the first heat insulation element 40 is located on the redistribution layer 10, and is arranged between the power device 30 and the first chip 20;

[0054] The first encapsulation layer 50, the first encapsulation layer 50 is disposed on the redistribution layer 10, and encapsulates the first chip 2...

Embodiment 2

[0062] The first thermal insulation element 40 is used to thermally isolate the power device 30 from the first chip 20, so as to prevent a large amount of heat generated by the power device 30 from being transmitted laterally to the first chip 20 on the same layer, affecting its working performance, thereby shortening the The lifetime of the first chip 20 improves the reliability of the packaging structure. And in practical application, the quantity of the first chip 20 can be multiple, please refer to figure 2 as shown, figure 2 It shows a schematic cross-sectional structure of a highly efficient heat dissipation multi-chip 3D stack package structure in Embodiment 2 of the present application. In this package structure, the first heat insulating element 40 can be arranged on the power device 30 and the power device 30 Between each adjacent first chip 20, that is, it is arranged on each side of the power device 30 adjacent to the first chip 20, and even the first heat insul...

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Abstract

The invention provides a multi-chip 3D stacked packaging structure with efficient heat dissipation and a packaging method. The structure comprises a rewiring layer; a first chip and a power device which are arranged on the rewiring layer and are electrically connected with the rewiring layer; a first heat insulation element which is positioned on the rewiring layer and is arranged between the power device and the first chip; a first packaging layer which is arranged on the rewiring layer and wraps and plastically packages the first chip, the first heat insulation element and the power device;an adapter plate which is arranged on the first packaging layer, wherein a second heat insulation element is arranged in the adapter plate; a second chip which is arranged on the adapter plate and iselectrically connected with the rewiring layer; and a second packaging layer which is arranged on the adapter plate and wraps and plastically packages the second chip. Thermal isolation is performed on the power device so that heat generated by the power device can be prevented from being transmitted to other chips in the transverse direction and the longitudinal direction, the power device is enabled to form an isolated heat source island and efficient heat dissipation can be realized.

Description

technical field [0001] The present application relates to the technical field of chip packaging, in particular to a multi-chip 3D stack packaging structure and packaging method with high heat dissipation. Background technique [0002] With the continuous improvement and development of integrated circuits, the volume is continuously reduced, the price is continuously reduced, and the functions are continuously improved. While improving the functions, the number of chips required by integrated circuits is increasing, and the design of semiconductor space is becoming more and more Rigorous and important. Since the stacked package can shorten the wiring length between chips, so as to achieve the purpose of shortening the delay time, easy to realize modularization and high speed, it is widely used. [0003] In the multi-chip stacking packaging process, due to the high integration of multi-chips, the heat treatment and heat dissipation of chips have become very important design p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/367H01L23/473H01L23/31H01L25/16H01L21/98
CPCH01L23/3107H01L23/367H01L23/473H01L25/16H01L25/50
Inventor 李潮罗绍根杨斌崔成强林挺宇
Owner 广东佛智芯微电子技术研究有限公司
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