FPGA layout legalization method utilizing regional relayout

Abstract

The invention discloses an FPGA arrangement legalization method utilizing regional rearrangement and belongs to the technical field of FPGAs. The method comprises the following steps of: abstracting an initial layout state according to regions to establish a residual graph, and assigning values to directed edges formed by abstracting a relationship between rearrangeable nodes and arrangeable positions in the residual graph by utilizing a line length to serve as the expenditure of the edges; based on the minimum expenditure and maximum flow algorithm, solving the residual graph to obtain the final legal position of each node. According to the method, the maximum flow algorithm is applied to the legalization part of the quadratic linear programming algorithm, so that the legalization processwhich does not have guidance originally has guidance; and the legal nodes and the arrangement positions occupied by the legal nodes also participate in modeling solution, so that the initial arrangement is optimized while legalization is carried out, the quality of the final solution is improved to a certain extent, the legalized line length is shorter, and the arrangement result is better.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a method for legalizing FPGA layout using regional re-layout. Background technique [0002] Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) is a chip widely used in household appliances, large machinery and even aerospace. The use of FPGA chips is inseparable from electronic design automation (Electronic Design Automation, EDA) tools. Layout is an important part of the EDA tool, which has a great impact on the running speed of the EDA tool itself and the final quality of the processed circuit. [0003] In recent years, the circuit scale of FPGA chips has grown rapidly, making its functions more powerful, but it has also brought challenges to the corresponding EDA tools. Analytical algorithms have become one of the mainstream directions of today's layout algorithms because they can use mathematical methods to quickly obtain the global optimal solution. The qua...

AI Technical Summary

Problems solved by technology

The quadratic linear programming algorithm is a kind of analytical algorithm. When it is specifically applied to solve the layout problem, it shows the characteristics of fast solution. However, after the solution is completed, there are still illegal layouts, such as the common overlapping node, so it needs to be legalized again

Although this method is simple and easy to implement, it does not have any guidance, and there are also the following problems in the selection, for example: if the location distance is marked by the Manhattan distance, can the location with the closest distance be better than the location with a long distance? There are multiple locations with the same Manhattan distance. Do these locations have the same advantages and disadvantages? These problems lead to the fact that although the original legalization process can quickly legalize the illegal layout, it cannot take into account the quality of the legalized layout, which often leads to unsatisfactory final solutions.

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