Excitation generation method for SOC system-level verification environment

Abstract

The invention discloses an excitation generation method for an SOC system-level verification environment. The method comprises: S1, analyzing an input file; analyzing a sub-module equipment model UVMinterface and the top layer of the SOC system-level verification environment, and establishing a connection relationship between the sub-module equipment model UVM interface and the top layer signal interface of the SOC system-level verification environment; S2, establishing an integrated verification environment; enabling a sub-module equipment model UVM environment to be quickly integrated intothe SOC system-level verification environment; and S3, performing simulation operation, and analyzing the result after operation. The method has the advantages that the principle is simple, operationis easy and convenient, the verification environment integration time can be shortened, and the SOC verification progress is accelerated.

Description

Technical field[0001]The present invention mainly relates to the technical field of chip verification, and specifically refers to a method for generating an incentive for an SOC system-level verification environment.Background technique[0002]The SOC system (System on Chip, system on chip) includes a processor core, an interconnect bus, and peripheral modules used to implement various functions. The traditional large-scale SOC system-level verification environment is developed based on the system verilog language. The main verification method in the SOC system-level verification environment is: write a C program or assembler to generate an executable binary file, and load the generated binary file into the memory device. , The processor reads the binary file from the memory device and executes it.[0003]With the increasing scale of SOC design, this traditional SOC system-level verification method can no longer meet the needs of current SOC verification. Its limitations are mainly refl...

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Problems solved by technology

[0003] With the increasing scale of SOC design, this traditional SOC system-level verification method can no longer meet the needs of current SOC verification. Its limitations are mainly reflected in: With the development of UVM (Universal Verification application, the module-level verification environment of peripheral modules is gradually implemented by UVM. These sub-module device models are relatively mature after module-level verification. If these mature sub-module device models can be integrated into the SOC system-level verification environment, it will effectively improve System-level verification environment development efficiency

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