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A processor replay debugging method and system

A processor and replay technology, applied in the direction of detecting faulty computer hardware, etc., can solve the problems of slow waveform recording of hardware emulation accelerators, affecting the simulation speed, and long debugging cycle, so as to speed up the chip verification process, speed up the verification process, The effect of improving the efficiency of software debugging

Inactive Publication Date: 2019-05-03
中科曙光信息产业成都有限公司 +1
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Problems solved by technology

[0003] At present, on the hardware emulation accelerator platform, the method of debugging the embedded software on the internal processor of the SoC is mainly by recording the waveform, but the waveform recording of the hardware emulation accelerator is slow, the debugging cycle is long, and the limited machine time is occupied, which seriously affects the simulation. speed

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  • A processor replay debugging method and system
  • A processor replay debugging method and system
  • A processor replay debugging method and system

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Embodiment Construction

[0014] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0015] The present invention provides a processor replay debugging system, which is applied to hardware emulation accelerators, such as figure 1 As shown, the system includes a system-on-a-chip including at least one processor and at least one transaction processing device corresponding to the at least one processor arranged on the host compu...

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Abstract

The invention provides a processor replay debugging method and system. The system comprises a host, a system-level chip and at least one transaction processing device, wherein the system-level chip and the transaction processing device are arranged on a hardware simulation accelerator and the system-level chip comprises at least one processor, and the transaction processing devices correspond to the at least one processor; The transaction processing device is used for recording key information in the program running process of the processor in real time and periodically sending the key information to the host; and the host is used for replaying the program execution process of the processor by utilizing the key information and a source program stored by the host so as to realize offline debugging of the processor. According to the invention, the transaction processing device is used for recording the key information in the program running process of the processor, and the recorded keyinformation is used for replaying the program execution process of the processor to realize offline debugging of the processor, so that the software debugging efficiency of the processor can be improved, and the chip verification process is accelerated.

Description

technical field [0001] The invention relates to the technical field of chip design and verification, in particular to a processor replay debugging method and system. Background technique [0002] With the increase of transistor scale, the design and verification of System On a Chip (SoC chip) face greater challenges, and the software simulation gradually reveals the disadvantage of slow speed. Hardware emulation accelerators are used more and more for their advantages of fast emulation speed and suitability for large-scale circuits. [0003] At present, on the hardware emulation accelerator platform, the method of debugging the embedded software on the internal processor of the SoC is mainly by recording the waveform, but the waveform recording of the hardware emulation accelerator is slow, the debugging cycle is long, and the limited machine time is occupied, which seriously affects the simulation. speed. Contents of the invention [0004] The processor replay debugging...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22
Inventor 李小波冉晓东杨金龙李文
Owner 中科曙光信息产业成都有限公司
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