Instruction processing device containing branch prediction loop, processor and processing method thereof

Abstract

The invention discloses an instruction fetching method. The method comprises the following steps of when a currently read instruction is a backward conditional branch instruction, determining whethera candidate instruction loop body indicated by the backward conditional branch instruction is consistent with an instruction loop body stored in a cache or not; if the candidate instruction loop bodyis consistent with the stored instruction loop body, taking out an instruction to be executed from the instruction loop body stored in the cache; and if the candidate instruction loop body is inconsistent with the stored instruction loop body, storing the candidate instruction loop body in a cache. The invention further discloses an instruction processing device for executing the method and a system-on-chip comprising the instruction processing device.

Description

technical field [0001] The present invention relates to the field of processors, in particular to a processor core and a processor including a loop register. Background technique [0002] Modern processors or processor cores process instructions in a pipelined fashion. A typical pipeline usually includes various pipeline stages such as instruction fetch, instruction decode, instruction issue, instruction execution and instruction retirement. Processors often include dedicated instruction fetch units to fetch instructions and feed them to the next stage of the pipeline. In order to continuously provide instructions to the next stage of the pipeline, the processor usually provides an instruction cache, and the instruction fetch unit usually continuously fetches instructions from the instruction cache to provide to the next stage. In order to fetch instructions from external memory devices or instruction cache, the instruction fetch unit consumes energy. Reducing the power c...

AI Technical Summary

Problems solved by technology

However, in practical applications, since the previously executed loop body has a high probability of needing to be executed again shortly after exiting the loop, the processing method of the existing scheme causes the same loop body to be filled repeatedly meaninglessly

In addition, in the existing instruction loop body scheme, the processing such as the jump prediction of the branch jump instruction in the loop body is generally not involved. In this way, for the branch jump instruction sent from the loop body buffer, its subsequent The determination of the instruction flow is error-prone and needs to be corrected in the subsequent stages of the pipeline, so that the branch and jump instructions from the loop body buffer can not be processed efficiently

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