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Readout circuit, and debugging method and device for readout circuit of memory chip

A technology for reading out circuits and memory chips, applied in information storage, static memory, digital memory information, etc., can solve the problems of high read error rate, comparator imbalance, inaccurate reference resistance resistance, etc., to reduce the read error rate. Effect

Active Publication Date: 2021-01-22
ZHEJIANG HIKSTOR TECHOGY CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The present application provides a readout circuit, a debugging method and device for a readout circuit of a memory chip, to solve the problem of the offset current in the comparator of the readout circuit of the memory in the related art, and the inaccurate resistance value of the reference resistor, resulting in a read error rate high problem

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  • Readout circuit, and debugging method and device for readout circuit of memory chip
  • Readout circuit, and debugging method and device for readout circuit of memory chip
  • Readout circuit, and debugging method and device for readout circuit of memory chip

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Embodiment Construction

[0030]It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other if there is no conflict. Hereinafter, the present application will be described in detail with reference to the drawings and in conjunction with embodiments.

[0031]In order to enable those skilled in the art to better understand the solutions of the application, the technical solutions in the embodiments of the application will be clearly and completely described below in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are only It is a part of the embodiments of this application, not all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the protection scope of this application.

[0032]It should be noted that the terms "first" and "second" in the description and claims of the ap...

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Abstract

The invention discloses a reading circuit, and a debugging method and device for the reading circuit of a memory chip. The readout circuit comprises a current comparator, the first input end of the current comparator is connected with the drain electrode of a first gating device, the grid electrode of the first gating device is connected with a clamping voltage, the source electrode of the first gating device is connected with a resistive memory unit, and the resistive memory unit stores a high-level signal or a low-level signal; the second input end of the current comparator is connected withthe drain electrode of a second gating device, reference voltage is connected to the grid electrode of the second gating device, and the source electrode of the second gating device is connected withan adjustable resistance circuit. According to the application, the problem of high reading error rate caused by offset current existing in a comparator of a reading circuit of a memory and inaccurate resistance value of a reference resistor in the prior art is solved.

Description

Technical field[0001]This application relates to the field of integrated circuit technology, and in particular to a method and device for debugging readout circuits and readout circuits of memory chips.Background technique[0002]In the existing MRAM readout circuit, a reference voltage (VREF) and a clamping voltage (VCLAMP) are added to the two input terminals of the sense amplifier SA, where VCLAMP provides voltage for the resistive memory cell (MTJ bit), and VREF A voltage is provided for the reference resistor Rref, so that the current flowing through the reference resistor Rref and the MTJ bit is compared through the sense amplifier SA to identify the high resistance state and the low resistance state of the MTJ bit.[0003]When testing the MRAM readout circuit, it is necessary to obtain the optimal VREF. Specifically, the read error rate curves in the high-resistance state and the low-resistance state are respectively obtained by adjusting the VREF, and the intersection of the two...

Claims

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Application Information

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IPC IPC(8): G11C11/16G11C13/00
CPCG11C11/1673G11C13/004Y02D10/00
Inventor 熊保玉沈岙卢欢哀立波
Owner ZHEJIANG HIKSTOR TECHOGY CO LTD