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Chip testing device

A chip testing and chip technology, applied in static memory, instruments, sorting, etc., can solve the problems of memory pin damage, low test efficiency, etc., and achieve the effect of reducing test time

Pending Publication Date: 2021-02-02
ONE TEST SYST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The embodiment of the present invention is to provide a chip testing device, which is used to improve the existing memory equipment. When the memory is tested in different temperature environments, it is necessary to repeatedly disassemble and assemble the chip, resulting in low test efficiency and easy to cause Memory pin damage problem

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Experimental program
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Embodiment Construction

[0049] Please also refer to figure 1 , figure 2 and image 3 , figure 1 It is a schematic diagram of the chip testing system disclosed by the present invention, figure 2 It is a schematic block diagram of the chip testing system disclosed by the present invention, image 3 It is a schematic diagram of the chip testing device disclosed in the present invention. The chip testing system E disclosed by the present invention is used for testing multiple chips C. The chip testing system E includes: a central control device E1, a chip mounting device E2, at least one chip testing device 1, a plurality of environmental control devices E3, a transfer device E4 and a sorting device E5.

[0050] The central control device E1 is connected to the chip mounting equipment E2, multiple environmental control equipment E3, transfer equipment E4, and sorting equipment E5, and the central control device E1 can control the operation of each equipment; the central control device E1 is, for e...

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PUM

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Abstract

The invention discloses a chip testing device. The chip testing device can be carried and transmitted among a plurality of workstations. The chip testing device comprises a circuit board, a control unit and a plurality of connecting terminals. The circuit board is provided with a plurality of electric connection seats, and each electric connection seat is used for bearing a chip. The control unitcomprises a plurality of test modules which are arranged on one side of the circuit board. The plurality of connection terminals is arranged on the circuit board. When the connection terminals are connected with an external power supply device, each test module is connected with the plurality of electric connection seats, and each test module can test chips carried by the electric connection seatconnected with the test module. After a plurality of chips is arranged on the plurality of electric connecting seats, the chips can be arranged in a high-temperature environment or a low-temperature environment together with the chip testing device for testing, and the chips do not need to be repeatedly disassembled and assembled.

Description

technical field [0001] The invention relates to a chip testing device, in particular to a chip testing device suitable for testing memory. Background technique [0002] Generally speaking, before the memory leaves the factory, it must pass a high temperature test, a burn-in test, or a high temperature test, a burn-in test and a low temperature test. Existing memory test equipment, when performing high temperature test, burn-in test or low temperature test, the memory must be repeatedly plugged and unplugged in different electrical connectors. It also wastes a lot of time and causes the problem of low test efficiency. Contents of the invention [0003] The embodiment of the present invention is to provide a chip testing device, which is used to improve the existing memory equipment. When the memory is tested in different temperature environments, it is necessary to repeatedly disassemble and assemble the chip, resulting in low test efficiency and easy to cause The memory ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56B07C5/344
CPCG11C29/56016B07C5/344
Inventor 蔡振龙基因·罗森塔尔
Owner ONE TEST SYST