Packaging method of semiconductor device
A packaging method, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of separation or warpage, heat sink and bar strain, etc.
Active Publication Date: 2021-04-02
度亘光电科技(南通)有限公司
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Problems solved by technology
[0003] The purpose of the present invention is to provide a packaging method for semiconductor devices, so as to alleviate the stress caused by the difference in thermal expansion between the bar and the heat sink in the prior art when the bar and the heat sink are soldered, and it is easy to make the heat sink and the bar Technical problem of creating strain between strips with risk of separation or warping
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[0040] The technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0041] Such as Figure 1 to Figure 15As shown, the semiconductor device packaging method provided in this embodiment includes the following steps:
[0042] Provide the first device, the second device, the buffer layer 300, the first solder layer 130 and the second solder layer 210; the melting point of the second solder layer 210 is lower than the melting point of the first solder layer 130, and the melting point of the first solder layer 130 is lower at the melting point of the buffer layer 300 ; wherein, one of the fi...
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Abstract
The invention provides a packaging method for a semiconductor device, which relates to the technical field of semiconductors and includes the following steps: providing a first device, a second device, a buffer layer, a first solder layer and a second solder layer; the second solder layer has a low melting point At the melting point of the first solder layer, the melting point of the first solder layer is lower than the melting point of the buffer layer; wherein, one of the first device and the second device is a heat sink structure, and the other is a bar structure. Soldering the first device and the buffer layer with the first solder layer in the first temperature range relieves a part of the stress, and then solders the second device and the buffer layer with the second solder layer in the second temperature range with a lower temperature , so that there is less welding stress between the first device and the second device, and the separation or warping of the heat sink structure and the bar structure is avoided. At the same time, the buffer layer arranged between the heat sink structure and the bar structure also It can further play the role of buffering the stress between the heat sink structure and the bar structure.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a packaging method for semiconductor devices. Background technique [0002] The heat sink and the bar of the existing semiconductor device are connected together by a layer of solder, wherein the heat sink is usually a copper heat sink, and the bar is made of gallium arsenide, the solder is placed between the two, and then passed together Heat to weld the bar and heat sink together. However, a copper heat sink has a coefficient of thermal expansion of 16.7E -6 / K, much larger than the thermal expansion coefficient of gallium arsenide bar 6.7E -6 / K, due to the large difference in expansion coefficient, it is easy to generate large stress during welding. In order to relieve the above pressure, a stress buffer structure is also arranged between the two in the prior art. Due to the heat sink, bar, stress buffer The structure and the solder between them are heated together ...
Claims
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IPC IPC(8): H01L21/60H01L21/50
CPCH01L21/50H01L24/83H01L2224/73265
Inventor 陈家洛陆翼森于学成赵卫东杨国文张艳春
Owner 度亘光电科技(南通)有限公司