Memory chip packaging structure and preparation method thereof

Abstract

The invention relates to a preparation method of a memory chip packaging structure. The method comprises the steps of arranging a first packaging layer, a first circuit layer, a first memory chip, a control chip and a second memory chip on a first carrier plate; arranging a second packaging layer, a second circuit layer, a third memory chip, a cache chip and a fourth memory chip on the first packaging layer; arranging a third packaging layer, a third circuit layer, a fifth memory chip and a sixth memory chip on the second packaging layer; then arranging a fourth packaging layer, a fourth circuit layer, a seventh memory chip and an eighth memory chip on the third packaging layer; and removing the first carrier plate, forming a plurality of first grooves for exposing the back surfaces of thememory chips in the packaging layers, forming a plurality of second grooves for exposing the first circuit layer in the first packaging layers, and forming heat dissipation columns and conductive columns in the first grooves and the second grooves respectively.

Description

technical field [0001] The invention relates to the field of packaging of semiconductor storage elements, in particular to a storage chip packaging structure and a preparation method thereof. Background technique [0002] With the continuous development of science and technology, people's demand for consumer electronic products is also increasing. The memory chip in electronic products is a key core component. In traditional memory packaging components, due to the limitation of the storage capacity of a single chip, Many layers of chips need to be stacked inside the memory packaging components to meet higher capacity storage requirements, 8 layers, 16 layers and 32 layers are already very common. Since the existing memory packaging components need to stack and package multiple chips inside, and in the existing packaging process, the increase in the number of stacked layers will significantly increase the process risk, and problems such as splits, tilts, or positional shifts ...

AI Technical Summary

Problems solved by technology

Since the existing memory packaging components need to stack and package multiple chips inside, and in the existing packaging process, the increase in the number of stacked layers will significantly increase the process risk, and problems such as splits, tilts, or positional shifts are prone to occur

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