Memory chip packaging structure and preparation method thereof

A memory chip and packaging structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as increased process risk, increased number of stacked layers, and inclination, so as to improve integration and functionality, Excellent electrical conductivity and cost reduction effect

Active Publication Date: 2021-02-12
湖南中科存储科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the existing memory packaging components need to stack and package multiple chips inside, and in the existing packaging process, the increase in the number of stacked layers will significantly increase the process risk, and problems such as splits, tilts, or positional shifts are prone to occur

Method used

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  • Memory chip packaging structure and preparation method thereof
  • Memory chip packaging structure and preparation method thereof
  • Memory chip packaging structure and preparation method thereof

Examples

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Embodiment Construction

[0019] It is to be appreciated that the following disclosure provides many different embodiments, or examples, for implementing different components of the presented subject matter. Specific examples of each component and its arrangement are described below in order to simplify the description of the disclosure. Of course, these are examples only and are not intended to limit the present disclosure. For example, the following disclosure describes that a first component is formed on or over a second component, which means that it includes the embodiment in which the first component is formed in direct contact with the second component, and also includes In addition, an additional component may be formed between the first component and the second component, so that the first component may not be in direct contact with the second component. In addition, different examples in the disclosure may use repeated reference signs and / or words. These repetitions or words are used for si...

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PUM

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Abstract

The invention relates to a preparation method of a memory chip packaging structure. The method comprises the steps of arranging a first packaging layer, a first circuit layer, a first memory chip, a control chip and a second memory chip on a first carrier plate; arranging a second packaging layer, a second circuit layer, a third memory chip, a cache chip and a fourth memory chip on the first packaging layer; arranging a third packaging layer, a third circuit layer, a fifth memory chip and a sixth memory chip on the second packaging layer; then arranging a fourth packaging layer, a fourth circuit layer, a seventh memory chip and an eighth memory chip on the third packaging layer; and removing the first carrier plate, forming a plurality of first grooves for exposing the back surfaces of thememory chips in the packaging layers, forming a plurality of second grooves for exposing the first circuit layer in the first packaging layers, and forming heat dissipation columns and conductive columns in the first grooves and the second grooves respectively.

Description

technical field [0001] The invention relates to the field of packaging of semiconductor storage elements, in particular to a storage chip packaging structure and a preparation method thereof. Background technique [0002] With the continuous development of science and technology, people's demand for consumer electronic products is also increasing. The memory chip in electronic products is a key core component. In traditional memory packaging components, due to the limitation of the storage capacity of a single chip, Many layers of chips need to be stacked inside the memory packaging components to meet higher capacity storage requirements, 8 layers, 16 layers and 32 layers are already very common. Since the existing memory packaging components need to stack and package multiple chips inside, and in the existing packaging process, the increase in the number of stacked layers will significantly increase the process risk, and problems such as splits, tilts, or positional shifts ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L21/56H01L21/60H01L25/18
CPCH01L21/4867H01L24/83H01L21/563H01L24/03H01L25/18H01L2224/0231H01L2224/02331H01L2224/02381H01L2224/83002H01L2224/18
Inventor 秦玲
Owner 湖南中科存储科技有限公司
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