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Analog processing circuit for metastable state in pre-simulation and pre-simulation method

A technology of analog processing and pre-simulation, which is applied in CAD circuit design, special data processing applications, etc., and can solve problems such as inability to monitor metastability

Pending Publication Date: 2021-03-02
SHANGHAI FINGER TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] figure 1 The pre-simulation (RTL simulation) is used as a behavioral simulation (functional simulation), which cannot detect the occurrence of metastable states. The designer does not know whether the asynchronous signal will be one beat ahead or one beat behind when the asynchronous circuit design is implemented, so it may There is a potential risk of alignment between control logic and data logic

Method used

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  • Analog processing circuit for metastable state in pre-simulation and pre-simulation method
  • Analog processing circuit for metastable state in pre-simulation and pre-simulation method
  • Analog processing circuit for metastable state in pre-simulation and pre-simulation method

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Embodiment Construction

[0031] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0032] The technical solution of the present invention will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0033] Please refer to Figure 6 , Figure 6 It is a schematic diagram of the simulat...

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Abstract

The invention discloses an analog processing circuit for metastable state in pre-simulation, which comprises a clock A, a first register R1, a second register R2 and a clock B. The first register R1 is provided with a first register signal input end, a first register signal output end and a first register clock end, and the pre-simulation analog processing circuit further comprises a third register R3 and a selector. According to the invention, simulation processing is carried out on the metastable state of the metastable state simulation processing circuit in pre-simulation, so that the designed chip circuit can tolerate the metastable state.

Description

technical field [0001] The invention belongs to the field of chip design, in particular to an analog processing circuit for metastable state in pre-simulation and a pre-simulation method for chip circuit tolerable metastable state. Background technique [0002] CDC (clock domain crossing, cross clock domain problem) signal refers to the signal transmitted from one clock domain to another asynchronous clock domain. If it is too close to the valid edge of the receive clock, then when the transmitted data changes within the setup / hold time (setup time / hold time) of the receive clock edge, the metastable state Metastability will occur, and the output of the sampling register will enter an indeterminate state. The metastable state will not only lead to logical misjudgment, but the output of the intermediate voltage value between 0 and 1 will also cause the next stage to generate a metastable state (that is, cause the propagation of the metastable state), and the propagation of th...

Claims

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Application Information

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IPC IPC(8): G06F30/33
CPCG06F30/33
Inventor 胡兵黄昊姜洪霖
Owner SHANGHAI FINGER TECH CO LTD