61 results about "Analog processing circuits" patented technology

A circuit comprising a digital processor, analogue processing means, a digital to analogue converter for converting digital values output from the digital processor into analogue values which are processed by the analogue processing means, and an analogue to digital converter for converting resulting analogue values into digital values for input to the digital processor, wherein the analogue processing means comprises one or more analogue processors, and the circuit is dynamically reconfigurable under the control of the digital processor, such that analogue values are processed according to a first function by the analogue processing means, and following reconfiguration, analogue values are processed according to a second function by the analogue processing means.

A first clamping unit clamps a base voltage of an input image signal to a predetermined reference voltage. A sampling-and-holding unit samples and holds the image signal after clamping or a reference signal that becomes the base voltage of the image signal. An amplifying unit amplifies the image signal sampled and held by the sampling-and-holding unit. An analog-to-digital converting unit converts the image signal after amplification into a digital image signal. A second clamping unit clamps the reference signal to a predetermined voltage.

Methods and apparatus for tuning are disclosed. One embodiment of the invention is directed to a tuner formed on a substrate. The tuner comprises a first die that receives an analog input signal and processes the analog input signal using analog processing circuitry to form analog output signals, and a second die that receives the analog output signals, converts the analog output signals to digital signals, and processes the digital signals to form output signals. Another embodiment of the invention is directed to a multi-chip module comprising a tuner adapted to process television signals of a plurality of types and of a plurality of standards to form output signals. A further embodiment of the invention is directed to a method that comprises receiving an analog signal from a signal source, filtering the analog signal to remove a portion of the analog signal, converting the analog signal to quadrature analog signals, converting the quadrature analog signals to digital signals, and filtering the digital signals to substantially isolate a channel of interest.

A driver apparatus is provided for controlling a light source array comprising at least first and second light sources, the light source array used for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. The driver apparatus comprises a single integrated circuit comprising processing means for processing image data received from the detector, a switching array comprising at least first and second switches for switching the respective first and second light sources, and a current source for controlling the flow of current through the light sources. In this way the LED switching circuitry that controls an LED array is placed on the same integrated circuit (i.e. monolithic circuit) as the analogue processing circuitry that processes the image data, with the current source controlling the flow of current through the LEDs in the LED array. The current source has the advantage of avoiding rapid changes or slope discontinuities in the current flowing through the LEDs, which would otherwise cause unwanted transient signals. A shunt path comprising a switching device may be provided in parallel with the LED array and switching array. The shunt path has the advantage of enabling the switching sequence from one LED to another to be controlled such that a substantially constant current is drained from the supply (subject to any differences in the inherent current drawn by the Red, Green and Blue LEDs, respectively).

An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.

An imaging device includes a pixel; a digital circuit; and an analog processing circuit including a constant current circuit, a current comparison circuit, and a control circuit. The pixel is capable of outputting differential data. The constant current circuit is capable of supplying a first current corresponding to the differential data, in accordance with a first control signal. The current comparison circuit is capable of supplying a second current that flows through the constant current circuit in accordance with a change in the differential data. The current comparison circuit has a function of setting a determination signal active depending on whether to supply the second current to the constant current circuit. The control circuit has a function of controlling the constant current circuit and the current comparison circuit to stop their functions as the determination signal becomes active. The digital circuit operates as the determination signal becomes active.

This invention discloses a car engine rotational velocity test device and a method including an analog process circuit and a converting circuit connected with the output of a microphone assembly and the input of a display circuit orderly, among which, the noise signal at the air vent is received by the microphone assembly and processed to become an engine rotational velocity signal or a value or a noise signal quantity value by the analog process circuit and the converting circuit. The analog process circuit includes a multiple selector for automatically controlling amplified output level to ensure a large dynamic sphere test and its accuracy.

The invention discloses a detection device of space electrons, which belongs to the field of detection of space charged particles. Equipment used by the device comprises a detector and a signal processing circuit, wherein the detector comprises a probe, a heavy metal housing and a metal base; and the probe mainly comprises a light-blocking sheet, a detection unit D1, a detection unit D2, a scintillator framework, a photomultiplier tube and an analog processing circuit board. According to a method disclosed by the invention, a space 0.1-1MeV electron energy spectrum can be detected; and the detector designed by utilizing the method has the characteristics of miniaturization, low power consumption, high resolution and high efficiency, and is convenient to be carried on a spacecraft for detection.

An RF receiver comprising a radio-frequency (RF) down-converter for receiving and down-converting an input RF signal to a lower frequency analog signal (e.g., an IF signal or baseband signal) and analog processing circuitry for receiving the lower frequency analog signal from the RF down-converter and outputting a processed analog signal. The processed analog signal includes a DC-offset signal introduced by the RF down-converter and the analog processing circuitry. The RF receiver also comprises an ADC circuit for converting the processed analog signal to a sequence of digital samples and a DC-offset correction circuit for detecting the DC-offset signal in a digital output signal of the RF receiver. The DC-offset correction circuit adds a DC-offset correction signal to the lower frequency analog signal. Adding the DC-offset correction signal to the lower frequency analog signal reduces the DC-offset signal in the processed analog signal at the analog processing circuitry output.

In order to reduce the frame rate, when all photodiodes contributing to output of a video signal in a CMOS image sensor must be simultaneously exposed (at the timing of strobe flashing Δts), as in a case where strobe is flashed, readout pixels composing the CMOS type image sensor are thinned such that the number of photodiodes contributing to the video signal outputted from the CMOS type image sensor is reduced. A time period Δtp2 required for processing (of the video signal caused by a row of photodiodes) in an analog processing circuit connected to the succeeding stage of the CMOS type image sensor is shortened, thereby reducing the frame rate.

An analog front-end circuit includes an analog processing circuit, an A / D converter, a calculation circuit, and a target register in which a black level target value is set. The analog processing circuit includes a clamp circuit that performs a line clamp operation, and an offset adjustment circuit. The calculation circuit monitors an A / D-converted value of a black reference pixel after the line clamp operation in a black level monitor period after a line clamp period but before an effective pixel output period, and performs a black level error correction process by writing an offset adjustment value that causes the A / D-converted value to be set at the black level target value into the offset adjustment register.

The invention discloses a concrete internal temperature detection device based on induction principle including the devices buried inside and outside of concrete. The internal device includes temperature sensor, the second CPU, modulation circuit and the second coil, which is used to receive and process the internal temperature information, and code the information for the signals external device can identify to send out. The external device includes the first coil, oscillation power amplification circuit, analog processing circuit, the first CPU and a communication interface, which are used to receive data from internal device, decode them to communicate with PC and provide energy for the internal device.

The invention discloses a rear-mounted mixing digital ALC (Automatic Level Control) system device based on a DDS. The device comprises the direct digital synthesizer DDS, a mixer, a filter unit, a power amplifier, a power allocation unit, a logarithmic detector, a voltage amplifier, an A / D collection chip and a digital processing unit. A PIN variable resistance diode or a numerical control attenuator in a traditional ALC system is replaced by the direct digital synthesizer DDS. The direct digital synthesizer DDS is mounted before the mixer unit. A complex analog processing circuit in the traditional ALC system is replaced by the data processing unit on a feedback circuit. The device has the advantages of good temperature stability, high amplitude stabilization precision and high bandwidth response and is applicable to the field of many test devices.

An analog front-end circuit includes an analog processing circuit, an A / D converter, and a timing generator that generates a plurality of control signals that are supplied to an image sensor. The timing generator includes an event information memory, and a control signal output circuit that generates the control signals based on information read from the event information memory and outputs the generated control signals. The event information memory stores a pixel number and change event occurrence information at each address. The change event occurrence information specifies a control signal that undergoes a signal level change event at the pixel number. The control signal output circuit generates the control signals based on the pixel number and the change event occurrence information read from the event information memory and outputs the generated control signals.

A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit 24. The imaging portion includes a pixel array 21 in which pixels 20 used for imaging and reference pixels 22 used for image processing are arranged in a matrix, and a row decoder 25. The arithmetic portion includes a memory element array 31 in which memory elements 30 and reference memory elements 32 are arranged in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.

A needle implantable atrial fibrillation monitor includes a plurality of terminals that generate a terminal voltage when the needle implantable atrial fibrillation monitor is implanted in a patient's body. An analog processing circuit generates a monitoring signal based on the terminal voltage. An analog to digital converter converts the monitoring signal to monitoring data. A processor analyzes the monitoring data, generates events and compresses the event data and that generates compressed data in response thereto. A memory stores the compressed data. An RF interface transmits the compressed data to a base station via RF signaling when the needle implantable atrial fibrillation monitor is implanted in the patient's body.

An electronic device that efficiently compresses a large volume of data included in a broadcast signal and stores the compressed data is to be provided. The broadcast signal is decoded and decompressed through a tuner and a set top box (STB), and a signal (image data) that is decoded and decompressed is inputted to a video display device, so that an image based on the signal is displayed. As a unit for efficiently compressing and storing the image, an electronic device including an encoder, a decoder, and a memory device is used. An image data outputted from the tuner and the STB is compressed using the encoder, and the compressed data is stored in the memory device. To reproduce and display the image data. the compressed image data is decompressed by the decoder, and the decompressed image data is inputted to the video display device. For the compression of the image data in the encoder, an analog processing circuit included in the encoder or a semiconductor device in which a neural network is constructed is used.

The invention discloses a fission chamber output signal digital processing system and a method thereof, relates to the technical field of nuclear reactor. The system contains a preamplifier circuit and a digital processing device, wherein the digital processing device contains a signal processing unit, a high-speed analog signal acquisition unit and a signal output unit. The high-speed analog signal acquisition unit is respectively connected with the preamplifier circuit and the signal processing unit and is used for acquiring an output signal of the preamplifier circuit and converting the output signal into a digital signal for outputting. The signal processing unit is connected with the high-speed analog signal acquisition unit and is used for determining the root-mean-square value of the digital signal acquiring neutron flux according to the root-mean-square value and a calibration coefficient of preset neutron flux measuring range. According to the invention, circuit is simplified, problems such as temperature drift of components and noise in the analogue processing circuit are avoided, precision of the measurement result is raised, and stability of the system is increased.

The invention provides a satellite network multifunctional common hardware reference platform and a control method thereof. The satellite network multifunctional common hardware reference platform comprises a common hardware reference platform, a CPU monitor and a human-computer interface, wherein the common hardware reference platform comprises a DSP (Digital Signal Processor) chip, an FPGA (Field Programmable Gate Array) chip, an FLASH storage chip and a communication module, the DSP chip is connected with the CPU monitor, the output of the DSP chip is connected with the input of the FPGA chip, the FLASH storage chip is connected with the DSP chip and the FPGA chip which is connected with the communication module, the communication module comprises a radio frequency receiving and transmitting channel, a filter and a channel amplification and analog processing circuit, the output of the channel amplification and analog processing circuit is connected with an analog-digital / digital-analog chip, the FPGA chip is connected with the output of the communication module, and the DSP chip and the FPGA chip process information of the receiving and transmitting channel. The invention ensures that an operator only knows one set of equipment operating process, and can ensure that resources of a plurality of satellite networks are more effectively utilized.

An absolute position measurement capacitive grating displacement measurement method, a sensor, and an operating method of the sensor are provided. In the measurement method, a drive signal having wave properties is used to excite a transmission grating, and displacement of a measured position in each wavelength is transformed into an initial phase of a time fundamental wave. The displacement of the measured position in each wavelength is acquired through an addition counter. A signal having wave properties output by a drive signal generator of the sensor is connected to a transmission grating, the master clock of an oscillator is connected to each circuit, an output of a reception grating is connected to a synchronous capture circuit through a signal selection switch and an analog processing circuit; and the synchronous capture circuit is connected to a controller, an addition counter, and a Random Access Memory (RAM). The controller is connected to all components. In the operating method of the sensor, an interface unit starts a measurement unit, a controller coordinates operation of all circuits, and after measurement of displacements in coarse, medium, and fine wavelengths is successively completed, the interface unit turns off the measurement unit, performs processing, and displays the measurement result. The circuits are simple, easy to control, and easy to be realized, and have high precision.

A measurement instrument comprises a sensor circuit comprising a drive circuit for transmitting a pulse signal at a target of interest and a receive circuit receiving reflected echoes of the pulse signal and developing an analog signal representative of the reflected echoes. An analog processing circuit is operatively coupled to the sensor circuit for receiving the analog signal and comprising a gate for selectively transferring the analog signal to a comparator that compares the gated analog signal to a select threshold level to develop a data signal representative of location of the target of interest. A programmed digital processing circuit is operatively coupled to the sensor circuit and the analog processing circuit and comprises a measurement module to control the drive circuit and evaluate the data signal to determine material location. An echo processing module periodically evaluates a digital representation of the analog signal to determine an expected window time and expected amplitude of a reflected echo representing the target of interest and developing a gate control signal to control the gate based on expected window time and developing the select threshold level based on the expected amplitude.

A process measurement instrument with target rejection comprises a sensor circuit. The sensor circuit comprises a drive circuit for transmitting a pulse signal at a target of interest and a receive circuit receiving reflected echoes of the pulse signal and developing an analog receive signal representative of the reflected echoes. An analog processing circuit receives the analog receive signal and comprises a summer subtracting an analog target rejection signal from the analog receive signal to develop a corrected receive signal. A programmed digital processing circuit is operatively coupled to the analog processing circuit and comprises a memory storing target rejection signal value data representing false target reflections and developing the analog target rejection signal for transfer to the analog processing circuit.

A thermocouple high-temperature testing system comprises a tungsten-rhenium thermocouple, an analogue processing circuit, an A / D converter, an SRAM (static random access memory) chip, a CPLD (complex programmable logic device) chip, a singlechip, a cool end compensation temperature sensor, a USB interface and a computer. The thermocouple high-temperature testing system provided by the invention is a miniaturized testing system which integrates a sensor, an adaptive magnifier, an A / D converter, a memorizer, a control circuit, an interface circuit and a minicell together. In the system, SRAM serves as a memorizer, after testing, data reading is achieved through the USB interface, and data information can be recorded, collected and measured objectively. The tungsten-rhenium thermocouple has the advantages of short responding time, wide measuring range, capability of testing a high-temperature section with the temperature higher than 2000 centigrade, simplicity and reliability in overall system operation, and accurate measurement, thereby being capable of ensuring the temperature measuring accuracy.

A hit command processing system for an electronic instrument includes: an angular velocity sensor; an analog processing circuit which receives the analog signal output from the angular velocity sensor, converts the analog signal into a digital signal, and outputs the digital signal as a rotational angular velocity value; a hit input detection section which receives the rotational angular velocity value output from the analog processing circuit, and determines whether or not a hit input is performed to an electronic instrument based on a change in the rotational angular velocity value; and a hit command execution section which executes a command associated with the hit input when the hit input detection section has determined that the hit input has been performed.

Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track- and-hold (T / H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with ''re-used'' or shared analog processing circuitry. Parallel track- and-hold (T / H) circuits (304, 306) receive an analog input signal (AIN or prior residue) and are clocked at half clock cycles (CLK / 2) by clocking circuit 303 to sample / hold on non- overlapping logic phases. The T / H circuits (304, 306) are respectively coupled to analog-to-digital converter (ADC 310) through multiplexer (308) and to digital-to-analog converter (DAC 312), adder (314) and amplifier (316) to perform analog processing to resolve sampled signals for digital output circuit (104) and to generate a residue signal (ROUT).