Data storage device, system-on-chip, radio device and equipment
A data storage device, system-level chip technology, applied in the field of data storage devices, radio devices and equipment, can solve problems such as difficult to write information and read correct information
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Embodiment 1
[0052] figure 1 It is a schematic structural diagram of the data storage device 100 provided in this application. The data storage device 100 provided in this embodiment can be used in a system-on-chip, see figure 1 As shown, the data storage device 100 may include modules such as a one-time programmable memory 101 and a read / write control module 102 .
[0053] Optionally, the data storage device 100 may further include at least one internal interface and at least one peripheral interface. The internal interface can be used to connect the internal processor 110 of the SoC, the read-write control module 102 and the one-time programmable memory 101 in order to form a first path, and the peripheral interface can be used to connect the external processor 120 of the SoC, The read-write control module 102 and the one-time programmable memory 101 are sequentially connected to form a second path. In the functional testing phase of the system-on-a-chip, the external processor 120 pe...
Embodiment 2
[0063] In order to write the memory repair information into the one-time programmable memory 101 during the wafer testing stage of the SoC. figure 2 It is a schematic structural diagram of the data storage device 200 provided in this application. The data storage device 200 provided in this embodiment can also be used in a system-on-a-chip, see figure 2 As shown, on the basis of the above embodiments, the data storage device 200 further includes: a memory repair module 201 and a first selection control module 202 . see figure 2 As shown, the first selection control module 202 is used to connect the memory repair module 201 with the one-time programmable memory 101 to form a third path. During the wafer test phase of the SoC, the memory repair module 201 can send the memory repair information to the one-time programmable memory 101 through the third channel.
[0064] in the design there are figure 2 In the case of the first selection control module 202 shown, the read-w...
Embodiment 3
[0067] image 3 It is a schematic structural diagram of the data storage device 300 provided in this application. The data storage device 300 provided in this embodiment can also be used in a system-on-chip, see image 3 As shown, on the basis of the above-mentioned embodiments, the data storage device 300 further includes: a second selection control module 301, the second selection control module 301 is used to connect any one of the peripheral interfaces and the internal interfaces with the The read / write control module 102 is connected to form the first path from the internal processor 110 to the one-time programmable memory 101 and the second path from the external processor 120 to the one-time programmable memory 101 described in the above embodiments.
[0068] Optionally, more ports can also be designed on the second selection control module 301, so that more processors can communicate with the one-time programmable memory 101 to form a path, so that more processors can...
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