Non-volatile memory device

Abstract

A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a secondmetal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line ina layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2019-0108469 filed with the Korean Intellectual Property Office on September 2, 2019, the entire disclosure of which is hereby incorporated by reference. technical field [0003] The inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device having a cell on peripheral (COP) structure. Background technique [0004] With recent multifunctionalization of information and communication equipment, memory devices are expected to have high capacity and high integration density. As memory cell sizes are reduced to achieve high integration density, operating circuits and / or interconnect structures included in memory devices for operation and electrical connection of the memory devices become complex. Therefore, memory devices having high integration density and excellent electrical characteristics are desired. In p...

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Problems solved by technology

The number of pass transistors connected to the word line may increase, increasing the die size

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