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TVM docking method and related equipment

A technology for electronic equipment and computational graphs, applied in the field of data processing, can solve the problems of slowing down the development progress of chips and slow running speed, and achieve the effect of reducing computing resource requirements, improving operating speed, and reducing computing resource requirements.

Pending Publication Date: 2021-03-19
SHENZHEN INTELLIFUSION TECHNOLOGIES CO LTD +1
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  • Abstract
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  • Claims
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Problems solved by technology

However, the introduction of TVM into the chip development environment will result in a very slow running speed and slow down the progress of chip development.

Method used

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  • TVM docking method and related equipment
  • TVM docking method and related equipment
  • TVM docking method and related equipment

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Embodiment Construction

[0039] Embodiments of the present application are described below with reference to the drawings in the embodiments of the present application.

[0040] see figure 1 , figure 1 It is a schematic structural diagram of a system for chip development provided by an embodiment of the present application. The system is applied to electronic equipment, and the system includes a TVM (Tensor Virtual Machine, vector virtual machine), a device connected to the TVM, and a chip development environment. Wherein, the TVM environment in the TVM may be the TVM environment of the historical project, or the original TVM environment. Wherein, the device connected to the TVM is connected to the TVM environment, and the device connected to the TVM includes:

[0041] A TVM correction module, configured to use TVM to generate a first calculation graph according to a target model, wherein the target model is used for chip development;

[0042] A calculation graph generating module, configured to ge...

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Abstract

The embodiment of the invention provides a TVM docking method and related equipment, and the method comprises the steps: employing a TVM to generate a first calculation graph according to a target model which is used for the development of a chip; and generating a second calculation graph according to the first calculation graph, wherein the structure of the second calculation graph is a calculation graph structure used for chip development, and the second calculation graph is input of a chip development environment. By adopting the embodiment of the invention, the operation resource requirement of TVM introduction on the chip development environment can be reduced, the operation rate is improved, and the operation time of the chip development environment is reduced.

Description

technical field [0001] The present application relates to the technical field of data processing, and in particular to a method for connecting to a TVM and related equipment. Background technique [0002] TVM (Tensor Virtual Machine, vector virtual machine) is an open source compiler framework that supports graphics processing unit (GPU), central processing unit (CPU), and field-programmable gate array (Field-Programmable Gate Array, FPGA) instruction generation. It is currently an open source project, mainly for the compiler stack of artificial intelligence deep learning system, or TVM is an open deep learning compiler stack for CPU, GPU and dedicated accelerator. The biggest feature of TVM is to optimize instruction generation based on graph and operator structure, and maximize hardware execution efficiency. TVM integrates quantization, which can improve efficiency during deep learning reasoning. TVM can be connected upward to deep learning frameworks such as Tensorflow,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/30G06F8/34
CPCG06F8/37G06F8/34Y02D10/00
Inventor 张丹黎立煌王和国
Owner SHENZHEN INTELLIFUSION TECHNOLOGIES CO LTD
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