Instruction processing device, processor and processing method thereof

Abstract

The invention discloses an instruction processing device which comprises an instruction reading and decoding unit, an instruction scheduling unit, an instruction execution unit and an instruction retirement unit. The instruction reading and decoding unit reads an instruction and decodes the read instruction, and caches the read and / or decoded instruction. The instruction scheduling unit receives and caches the decoded instruction, and transmits the received instruction to the instruction execution unit for execution. And the instruction execution unit receives the instruction transmitted fromthe instruction scheduling unit and executes the instruction. The instruction retirement unit caches the instructions executed by the instruction execution unit and retirees the instructions. The instructions comprise a speculation execution instruction and a speculation condition judgment instruction. The speculative execution instruction is an instruction to be executed when the speculative condition is assumed to be correct, and when a result of execution of the speculative condition judgment instruction in the instruction execution unit indicates that the speculative condition is wrong: instructing the instruction reading and decoding unit to clear the cached read and / or decoded instruction; instructing an instruction scheduling unit to clear the cached instruction after the retirementspeculation condition judgment instruction; and instructing the instruction execution unit to clear the instruction executed therein and clear the instruction cached in the instruction retirement unit after the instruction older than the speculation condition determination instruction is executed and retireed. The invention further discloses an instruction processing method executed in the instruction processing device and a system-on-chip comprising the instruction processing device.

Description

technical field [0001] The present invention relates to the field of processors, in particular to processor cores and processors for speculative execution. Background technique [0002] Modern processors or processor cores process instructions in a pipelined fashion. A typical pipeline usually includes various pipeline stages such as instruction fetching, instruction decoding, instruction scheduling, instruction execution, and instruction retirement. In today's multi-issue high-performance processors, in the instruction decoding stage, multiple instructions can be sequentially decoded within the same clock cycle, and then in the instruction scheduling stage, the sequentially decoded instructions are determined according to the instruction type and pipeline The downstream instruction execution state sends instructions out of order to each instruction execution stage, so that multiple instructions are executed simultaneously in the instruction execution stage. Finally, in th...

AI Technical Summary

Problems solved by technology

This traditional method will cause the instruction fetch request of the correct path to be issued later, delay the execution time of the instruction of the correct path, and then reduce the performance of the processor in the speculative failure scenario

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