Simulation verification method and system based on combination of virtual platform and FPGA

Abstract

The invention discloses a simulation verification method and system based on combination of a virtual platform and an FPGA, and the method comprises a verification step: constructing a first conversion model, receiving a simulation request of a host model through the virtual platform based on TLM2.0, and converting the simulation request into a first data package; constructing an FIFO switching verification model according to a third-party PCIe DMA method, and simulating a data transceiving channel; constructing a second conversion model, receiving the first data packet, performing analysis according to a preset protocol, and sending an analysis result to an RTL design DUT according to an AHB / AXI protocol; and a simulation step: generating an executable file according to the host model andthe second conversion model, storing the executable file in an upper computer for simulation, generating a burning file according to a third-party PCIe DMA method, the first conversion model and RTLdesign DUT, downloading the burning file to the FPGA, and enabling the upper computer to run the executable file to be connected with the FPGA for joint simulation. According to the method and system,the economic cost and the verification cost of simulation are greatly reduced, and a user can conveniently and flexibly optimize and modify according to actual requirements.

Description

technical field [0001] The invention relates to the technical field of simulation verification, in particular to a simulation verification method and system based on the combination of a virtual platform and FPGA. Background technique [0002] As the performance of SoC chips is getting higher and higher, and the design scale is getting larger and larger, the RTL simulation speed based on traditional EDA tools can no longer meet the project cycle requirements. At present, simulation through software and hardware collaboration has become a common practice in the industry. One of the methods is to use EDA tools for pure software mixed simulation based on CPU / GPU / DSP functional models and RTL design. However, if the scale of RTL design is large , its simulation speed is too slow, often unacceptable. Another method is to realize software-hardware co-simulation through a virtual platform and a hardware accelerator, but the annual cost of using a hardware accelerator, which is as ...

AI Technical Summary

Problems solved by technology

[0002] As the performance of SoC chips is getting higher and higher, and the design scale is getting larger and larger, the RTL simulation speed based on traditional EDA tools can no longer meet the requirements of the project cycle.

At present, simulation through software and hardware collaboration has become a common practice in the industry. One of the methods is to use EDA tools for pure software mixed simulation based on CPU / GPU / DSP functional models and RTL design. However, if the scale of RTL design is large , its simulation speed is too slow, often unacceptable

Another method is to realize software-hardware co-simulation through a virtual platform and a hardware accelerator, but the cost of using a hardware accelerator, which is as high as one million U.S. dollars per year, is unaffordable for small and medium-sized chip companies.

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