The invention discloses a
Layout collaborative design method for a super-large-scale
wafer-level substrate, and the method comprises the steps: loading all devices into a substrate, and enabling a
network connection relation to be consistent with a
netlist; the devices are arranged according to the
network connection relation and the position requirement, and the substrate is divided into corresponding parts through dividing lines according to the number of designers of common design; opening interconnected fly lines of all parts and performing highlighting treatment; a wiring layer of
interconnection lines is planned, each designer processes a corresponding part, all other devices are deleted, and a board frame is reserved; enabling the designers to walk the
interconnection lines to a segmentation line area, aligning the
interconnection lines in a manner of adjusting grid points, and completing the rest of wiring; the designer exports the designed substrates into files matched with the third-party
software; placing the lines in each file in a graph in a
copying manner; and completely connecting the disconnected interconnection lines by using a third-party
software line drawing command. According to the method, in the
design process, the jamming condition hardly occurs, the design efficiency is improved, and the project period is shortened.