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Chip design method based on RISC-V, navigation chip and receiver

A RISC-V and chip design technology, applied in CAD circuit design, computer-aided design, computing, etc., can solve problems such as insufficient to meet the pursuit of low power consumption, achieve high versatility, reduce chip power consumption, and reliability Good results

Active Publication Date: 2021-04-02
长沙金维信息技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The traditional method of reducing power consumption has been implemented as a specification and standard in many IC design companies. However, with the development of technology and the requirements of equipment, the traditional method of reducing power consumption is no longer enough to meet people's needs for low power consumption. Pursue

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  • Chip design method based on RISC-V, navigation chip and receiver
  • Chip design method based on RISC-V, navigation chip and receiver

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Embodiment Construction

[0028] Such as figure 1 Shown is the method flow diagram of the method of the present invention, as figure 2 Shown is a schematic diagram of the internal architecture of the chip designed by the method of the present invention: the RISC-V-based chip design method provided by the present invention includes the following steps:

[0029] S1. Divide the inside of the chip into a power supply part, a large system part and a small system part;

[0030] S2. The power supply part supplies power to the designed chip;

[0031] S3. Design the main core, large system bus bridge and several large system submodules in the large system part; the main core and several large system submodules are connected through the large system bus bridge; the large system part is used to complete all of the designed chip Function;

[0032] The main core can adopt mainstream high-performance CPU, which is responsible for the main functions of the chip;

[0033] S4. Design RISC-V core, small system bus ...

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Abstract

The invention discloses a chip design method based on RISC-V. The chip design method comprises the following steps: dividing the interior of a chip into a power supply part, a large system part and asmall system part; the power supply part supplies power; a main core, a large system bus bridge and a plurality of large system sub-modules are designed in a large system part and used for completingall functions of a chip; an RISCV core, a small system bus bridge and a plurality of small system sub-modules are designed in a small system part and used for power consumption management and auxiliary work after a main core is powered down. And the large system bus bridge and the small system bus bridge are connected and carry out communication and data interaction. The invention also discloses anavigation chip designed by adopting the chip design method based on RISC-V. The invention also discloses a receiver comprising the navigation chip and a chip design method based on RISC-V. The powerconsumption of the chip can be effectively reduced, the universality is high, and the reliability is good.

Description

technical field [0001] The invention belongs to the field of chip design, and in particular relates to a RISC-V-based chip design method, a navigation chip and a receiver. Background technique [0002] With the development of economy and technology, chip design has been extensively developed. With the reduction of process feature size and the increase of complexity, the power consumption density per unit area of ​​the chip has risen sharply, and has reached the limit that packaging, heat dissipation, and underlying equipment can support; heat dissipation and reliability issues also require IC performance. The smaller the consumption, the better. For the current popular mobile devices, the complexity of SoC design is getting bigger and bigger, and the requirements for power consumption are getting higher and higher. In the chip design industry, low-power technologies emerge in an endless stream, and major chip companies are paying more and more attention to them. The low-po...

Claims

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Application Information

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IPC IPC(8): G06F30/33G06F115/02
CPCG06F30/33G06F2115/02
Inventor 谷佳华刘彦张玉安丁杰李春雷刘亮亮
Owner 长沙金维信息技术有限公司
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