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Equalizer for high-speed interface circuit and its control method

A high-speed interface, equalizer technology, applied in the direction of shaping network, electrical components, digital transmission system in transmitter/receiver, etc., can solve the channel bit error rate increase, data edge jitter, can not meet high-speed data transmission, etc. problem, to achieve the effect of reducing data jitter, reducing design difficulty, and simple structure

Active Publication Date: 2022-06-28
玄武石半导体(武汉)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the expansion of demand for high-speed signal processing technology, the intersymbol interference (InterSymbol Interference, ISI) generated during signal transmission has become a technical difficulty restricting the increase in signal rate. increase
[0003] In the existing equalizer technology, the clock CLK with the same signal rate needs to be used, and the delay module is also limited by the current process conditions, which cannot meet the needs of high-speed data transmission

Method used

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  • Equalizer for high-speed interface circuit and its control method
  • Equalizer for high-speed interface circuit and its control method
  • Equalizer for high-speed interface circuit and its control method

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Embodiment 1

[0030] Embodiment 1 of the present invention provides an equalizer for a high-speed interface circuit, such as Figure 1-3 As shown, it includes a linear equalizer module 1 for receiving and primary balancing input signals, an adder compensation module 2, a decision delay module 3 and a coefficient adjustment module 4, and the linear equalizer module 1 is sequentially connected to the adder compensation module 2 , a decision delay module 3 and a coefficient adjustment module 4, the adder compensation module 2 combines the input signal after the primary balance of the linear equalizer module 1 with the multi-channel equalized signal for addition processing and then selects the output through the channel, and the decision delay The module 3 selects and outputs the signal of the adder compensation module 2 channel according to the control signal, and then outputs it to the adder compensation module 2 through the channel selection. The coefficient weighting adjustment is output to...

Embodiment 2

[0048] Embodiment 2 of the present invention provides a method for controlling an equalizer applying the high-speed interface circuit, including the following steps:

[0049] S1. The linear equalizer module receives and primary balances the input signal;

[0050] S2, the adder compensation module performs addition processing on the primary balanced input signal in S1 combined with the multi-channel equalized signal, and then selects the output through the channel;

[0051] S3, the decision delay module performs the decision delay of the signal output by the channel selection in the S2 according to the control signal CLK, and then outputs the signal to the adder compensation module through the channel selection;

[0052] S4. The coefficient adjustment module performs coefficient weighting adjustment on the decision-delayed signal in S3 and outputs it to the adder compensation module.

[0053] In the control method of the equalizer of the high-speed interface circuit of the pre...

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Abstract

The invention discloses an equalizer of a high-speed interface circuit and a control method thereof, wherein the equalizer of the high-speed interface circuit includes a linear equalizer module, an adder compensation module, a decision delay module and a coefficient adjustment module. In the equalizer of a high-speed interface circuit of the present invention, the input signal after the primary balance of the linear equalizer module is combined with the multi-channel equalization signal for addition processing through the adder compensation module, and then output through channel selection, and the adder through the decision delay module The signal output by the channel selection of the compensation module is judged and delayed according to the control signal, and then output to the adder compensation module through channel selection, and the coefficient adjustment module is used to adjust the coefficient weighting of the judgment delay signal of the judgment delay module, and then output to the adder compensation module , so as to reduce the data jitter of high-speed signals. Compared with the traditional method, the structure of the delay module is simpler, the design difficulty is reduced, and it is easier to implement under the existing process conditions.

Description

technical field [0001] The invention belongs to the technical field of high-speed communication, and in particular relates to an equalizer of a high-speed interface circuit and a control method thereof. Background technique [0002] The rapid development of the Internet has created a demand for big data and large traffic. This also contributes to the continued growth of bandwidth requirements. With the expansion of the demand for high-speed signal processing technology, the InterSymbol Interference (ISI) generated in the process of signal transmission has become a technical difficulty restricting the increase of the signal rate. ISI will cause jitter on the data edge and lead to the bit error rate of the channel. increase. [0003] In the existing equalizer technology, a clock CLK with the same signal rate needs to be used, and at the same time, the delay module is also limited by the current process conditions and cannot meet the requirements of high-speed data transmissi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L25/03
CPCH04L25/03267H04L25/03012H04L25/03006
Inventor 郭玉华
Owner 玄武石半导体(武汉)有限公司
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