Chip packaging structure and preparation method thereof

A packaging structure and chip technology, used in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices, etc., can solve problems such as deformation, short-circuit, and device performance failure of metal wires.

Inactive Publication Date: 2021-04-16
厦门通富微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the metal line width is less than 5 μm, deformation, short-circuiting, breakage, etc. are prone to occur between the metal lines, resulting in device performance failure

Method used

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  • Chip packaging structure and preparation method thereof
  • Chip packaging structure and preparation method thereof
  • Chip packaging structure and preparation method thereof

Examples

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preparation example Construction

[0037] In one aspect of the present invention, as figure 1 As shown, a method S100 for preparing a package structure of a chip is provided, and the method S100 includes:

[0038] S110, providing a carrier sheet.

[0039] Exemplary, combined with figure 2 , providing a carrier sheet 110, the carrier sheet 110 includes a first surface 111 and a second surface 112 oppositely arranged along its thickness direction. In this step, the carrier sheet 110 can be a flat plate made of silicon, glass, metal, organic substrate, etc. Those skilled in the art can also choose carrier sheets of other materials according to actual needs, which is not limited in this embodiment.

[0040] S120, sequentially forming at least one first passivation layer and at least one second passivation layer on the first surface of the carrier sheet along its thickness direction, the second passivation layer and the first passivation layer Alternate interval settings.

[0041] Exemplarily, in this step, a l...

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Abstract

The invention provides a chip packaging structure and a preparation method thereof. The method comprises the following steps: providing a bearing sheet; sequentially forming at least one first passivation layer and at least one second passivation layer on the first surface of the bearing sheet in the thickness direction of the bearing sheet, wherein the second passivation layers and the first passivation layers are alternately arranged at intervals; patterning the first passivation layer to form a first via hole, and forming a metal layer in the first via hole, wherein the thickness of each metal layer is greater than the thickness of the corresponding first passivation layer; removing the metal higher than the first passivation layer, enabling the remaining metal layer to be flush with the corresponding first passivation layer, and obtaining each metal wiring; patterning the second passivation layer to form a second via hole, wherein the metal wirings are electrically connected through the second via hole; and forming a metal bump on the second passivation layer on the topmost layer, wherein the metal bump is electrically connected with each metal wire through the second via hole. According to the invention, the surfaces of the metal wiring and the corresponding first passivation layer are smooth, the precision of the first passivation layer is improved, and the minimum wire width of the metal wiring can be 1 [mu]m.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a chip packaging structure and a preparation method thereof. Background technique [0002] With the diversification of electronic products, devices of various sizes are in demand. The preparation of filters, transformers, capacitors, inductors and other devices with micron-scale line width is limited by the height of metal bumps, so that the photoresist covers the metal The surface behind the bump is uneven, and the metal line width must be greater than 5 μm to meet the manufacturing requirements. When the metal line width is less than 5 μm, deformation, short-circuiting, breakage and the like are prone to occur between the metal lines, resulting in failure of device performance. Contents of the invention [0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a chip packaging structure and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L23/498
Inventor 张文斌
Owner 厦门通富微电子有限公司
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