Reconstruction method of ZYNQ chip single-point connection quickIO bus

Abstract

The invention discloses a reconstruction method for a single-point connection quickIO bus of a ZYNQ chip, and aims to provide a reconstruction design thought for a single-point connection quickIO link of an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) program, which is low in labor cost, high in joint test efficiency and low in software coupling. According to the technical scheme, a monitoring program is started after a ZYNQ program is loaded, the conditions of first-time loading and dynamic loading of an FPGA and a DSP program are monitored in parallel in real time, after any one of the FPGA and the DSP program is loaded, the FPGA and the DSP enter an external reset process, and then when the FPGA and the DSP program are switched into the reset release process, the FPGA program starts to work before the DSP program; dSP reset release is later than FPGA reset release, so that a fixed quickIO link sequence relationship exists after loading of an FPGA and a DSP program, and reconstruction of a single-point connection quickIO link is realized through ZYNQ chip control.

Description

Technical field[0001]The present invention relates to a radar and communication related field, and the reconstruction method of the FPGA + DSP single point connection RAPIDIO bus is realized by ZynQ chip control.Background technique[0002]With the rapid development of communication and network technology, in the embedded system, the DSP algorithm for increasing the amount of operation and real-time requirements, the processing capabilities of the DSP processor, and the internal chip parallel processing capabilities Higher requirements have gradually become mainstream configuration using the FPGA + DSP hardware architecture. The low-speed EMIF bus used between the DSP processor and the peripheral device is gradually replaced by a high-performance interconnected architecture Rapidio bus.[0003]In the existing system through the Rapidio bus single-point connection, the FPGA is loaded with the DSP program. Especially when one of the two programs reaches the curing state, it is necessary t...

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Problems solved by technology

[0004] The purpose of the present invention is to aim at the deficiencies existing in the prior art, to provide a kind of low manpower cost, high joint test efficiency, low software coupling, ZYNQ chip single-point connection RapidIO bus reconfiguration method, to solve the problems in the existing system There is a sequential relationship between FPGA and DSP program loading and its coupling relationship when using the RapidIO bus to improve the efficiency of system joint test integration

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