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A hardware acceleration system and method based on 3D scene design

A hardware acceleration and scene technology, applied in the computer field, can solve the problems of not being able to quickly display 3D scene works in real time, increase design costs, and consume large storage resources, so as to achieve high-precision real-time effects

Active Publication Date: 2022-06-07
成都视海芯图微电子有限公司
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  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is that in the calculation process of the existing virtual 3D scene design, it involves calculations such as text processing, image processing, attention calculation, knowledge base retrieval, graph neural network, etc., and there are problems of complex calculation and large consumption of storage resources , in the team design or the user's own scene construction, the terminal device cannot quickly display and interact with the designed virtual 3D scene works in real time, resulting in long design cycle, high design cost and poor user experience

Method used

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  • A hardware acceleration system and method based on 3D scene design
  • A hardware acceleration system and method based on 3D scene design
  • A hardware acceleration system and method based on 3D scene design

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Embodiment

[0038] as Figure 1 As shown, the present invention is a hardware acceleration system and method based on a 3D scene design, Figure 1 is a schematic diagram of the architecture of the hardware acceleration system of the real-time 3D scene design of the present invention, such as Figure 1 As shown, the system comprises, the main processor 11, the main memory 12, the acceleration device 13, wherein the acceleration device comprises a cache module 131, a pulse array module 132, a PE array module 133, a scalar computing module 134, an activation function module 135, an embedding computing module 136, a softmax computing module 137, a controller module 138, wherein the cache module 131 includes an input cache module a and an output cache module b.

[0039] The main processor 11, the main memory 12, the controller module 138 is connected, the acceleration device is generated to execute the command for the accelerated algorithm, and the generated command is passed to the controller module...

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Abstract

The invention discloses a hardware acceleration system and method based on 3D scene design, including the acceleration device, a main processor and a main memory, and the acceleration device includes a cache module, a controller module, an embedding calculation module, a PE array module, A systolic array module, a scalar calculation module, an activation function module, and a softmax calculation module. The cache module includes an input cache module and an output cache module, which can effectively implement feature extraction for pictures and text, attention coding, and external knowledge base retrieval. Graph neural network reasoning and layout optimization can realize accelerated processing of high-precision real-time 3D scene design.

Description

Technical field [0001] The present invention relates to the computer field, specifically to a hardware acceleration system and method based on a 3D scene design. Background [0002] With the continuous improvement of people's living standards and the development of visual processing technology, the demand for 3D scene visualization services is constantly improving, there are currently a series of methods for 3D scene designers to provide scene design and layout, however, because the virtual 3D scene design in the calculation process, involving text processing, picture processing, attention calculation, knowledge base retrieval, graph neural network and other calculations, there is a problem of complex computing, storage resource consumption, in the team design or the user's independent scene construction The terminal device cannot quickly display and interact with the virtual 3D scene works designed in real time, resulting in a long design cycle, increased design costs, and poor ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/40G06T15/00G06N3/08G06N3/04
CPCG06T1/20G06T15/00G06N3/08G06N3/045Y02D10/00
Inventor 张旻晋许达文
Owner 成都视海芯图微电子有限公司
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