A fpga-based national secret algorithm acceleration processing system

Abstract

The invention discloses an FPGA-based national secret algorithm acceleration processing system, which is used for processing the data packets sent to the server that need to be processed by the national secret algorithm. The system includes an FPGA that is connected to the server through a PCIE core interface. The FPGA is used to transfer the data packets in the server memory that need to be processed by the national secret algorithm through the PCIE core interface to the large-capacity cache DDR of the FPGA through the DMA read operation, and realize the required national secret algorithm through the corresponding user-defined national secret algorithm IP core The processing of the processed data packets forms the data packets processed by the national secret algorithm and transmits them to the DDR, and transmits the data packets processed by the national secret algorithm in the DDR to the server-side memory through the PCIE core interface through the DMA write operation. The accelerated processing system of the present invention has good reusability and expandability, and has good popularization and use value.

Description

technical field [0001] The invention relates to the field of network information security, in particular to an FPGA-based national secret algorithm acceleration processing system. Background technique [0002] With the continuous development of Internet technology, people are increasingly dependent on the network environment and network information resources, and information security issues have become the top priority of maintaining network security. The national secret algorithm issued by the National Security Bureau is a commercial encryption algorithm and specification independently developed by China, including the public SM2, SM3, and SM4 algorithms, which are used to ensure the security of commercial encryption. Today, more and more cryptographic chips are used in smart cards. How to effectively protect the security of smart cards through national secret algorithms and complete corresponding cryptographic tasks more efficiently has become a recent research hotspot in ...

AI Technical Summary

Problems solved by technology

[0011] To sum up, the current hardware platforms for cryptographic acceleration processing mainly have the disadvantages of low throughput and poor scalability.

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