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Data transmission interface circuit and data transmission method thereof

A technology of data transmission interface and data transmission method, which is applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of too many bus transceivers, waste of channel resources, and increased circuit complexity.

Active Publication Date: 2021-05-07
CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method occupies more bus transceivers, but the actual bus transceivers will waste channel resources
In addition, this design has high requirements for hardware, which increases the complexity of the circuit.

Method used

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  • Data transmission interface circuit and data transmission method thereof
  • Data transmission interface circuit and data transmission method thereof
  • Data transmission interface circuit and data transmission method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] see figure 1, is a schematic diagram of the data transmission interface circuit provided by Embodiment 1 of the present invention. In this implementation, the data transmission interface circuit includes: a programmable logic unit 1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a bus transceiver unit 2, and a data transceiver unit 3, so The bus transceiver unit 2 includes a first channel 21 and a second channel 22 . In some of these embodiments, the programmable logic unit 1 is a Field Programmable Gate Array (Field Programmable Gate Array, FPGA), the bus transceiver unit is an in-phase bus transceiver (such as SN74ALVC164245 chip), and the data transceiver unit is Analog-to-digital converter (such as AD7712 chip).

[0039] In some of these embodiments, through an FPGA-based programmable gate array, the hardware VHDL language can be used to program and complete asynchronous bidirectional signal transmission (the program inside ...

Embodiment 2

[0051] see figure 2 , is a data transmission flowchart of the data transmission method provided in Embodiment 2 of the present invention. In this embodiment, according to different requirements, figure 2 The order of execution of the steps in the flowcharts shown may be changed, and certain steps may be omitted. in, figure 2 The data transfer method shown applies to the figure 1 The data transmission interface circuit.

[0052] Step S10: When the bus transceiver unit 2 receives the data transmission signal of the data transceiver unit 3, control the enable control port (OE1) of the first channel 21 of the bus transceiver unit 2 to pass through the first resistor R1 Pull it to the power supply VDD, so that the bus transceiver unit 2 is in a high impedance state during the power-on initialization process, thereby reducing the power-on current of the bus transceiver unit 2 .

[0053] Step S11: Control the first enable control port (FOE1) of the programmable logic unit 1 t...

Embodiment 3

[0059] see image 3 , is a data receiving flowchart of the data transmission method provided in Embodiment 3 of the present invention. In this embodiment, according to different requirements, image 3 The order of execution of the steps in the flowcharts shown may be changed, and certain steps may be omitted. in, image 3 The data transfer method shown applies to the figure 1 The data transmission interface circuit.

[0060] Step S20: When the bus transceiver unit 2 receives the data transmission signal of the data transceiver unit 3, control the enable control port (OE2) of the second channel 22 of the bus transceiver unit 2 to pass through the third resistor R3 Pull it to the power supply VDD, so that the bus transceiver unit 2 is in a high impedance state during the power-on initialization process, thereby reducing the power-on current of the bus transceiver unit 2 .

[0061] Step S21: Control the second enable control port (FOE2) of the programmable logic unit 1 to se...

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Abstract

The invention provides a data transmission interface circuit, which comprises a programmable logic unit, a first resistor, a second resistor, a third resistor, a fourth resistor, a bus transceiving unit and a data transceiving unit, and is characterized in that the bus transceiving unit comprises a first channel and a second channel; when a data port of the data transceiving unit is in a sending state or the data sending port of the programmable logic unit is in a working state, the data receiving port of the programmable logic unit is set to be in a high-resistance state; and when the data port of the data transceiving unit is in a receiving state or the data receiving port of the programmable logic unit is in a working state, the data transmitting port of the programmable logic unit is set to be in a high-resistance state. In addition, the invention also provides a data transmission method. According to the invention, the complexity of hardware circuit design can be simplified, and element resources are saved.

Description

technical field [0001] The invention relates to the technical field of data transmission interface circuit design, in particular to an interface circuit for multi-channel asynchronous bidirectional data transmission and a data transmission method thereof. Background technique [0002] Currently commonly used bus transceivers usually contain two independent power rails, such as TI's SN74ALVC164245 chip is a 16-bit (double octal) non-inverting bus transceiver. The A port of this transceiver has a supply voltage VCCA, which is set to operate at 2.5V and 3.3V, allowing conversion from 2.5V to 3.3V and vice versa. The transceiver's B port has a supply voltage of VCCB and is set to operate at 3.3V and 5V, allowing conversion from 3.3V to 5V and vice versa. The transceiver is mainly designed for communication between asynchronous data buses. Its control pins (1DIR, 2DIR, 1OE and 2OE) are powered by the supply voltage VCCA to ensure a high-impedance state during power-on initializa...

Claims

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Application Information

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IPC IPC(8): G06F13/38G06F13/40
CPCG06F13/387G06F13/4068Y02D10/00
Inventor 孙振亚刘栋斌赵越李巍李哲刘衍峰王小朋高志良张达
Owner CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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