Defect detection wafer graph optimization method and optimization system thereof

Abstract

The invention provides a defect detection wafer graph optimization method and an optimization system thereof. The defect detection wafer graph optimization method comprises the following steps of: performing defect detection on a wafer through a machine end to obtain a wafer graph; carrying out probe testing on each chip on the wafer, and importing probe testing data of the chips into the machine end; generating a wafer probing map according to the probing data of each chip; and making the proportion and coordinates of the wafer prober map and the wafer map consistent so as to compare the wafer prober map and the wafer map, and marking chips which are not in the wafer prober map in the wafer map. According to the defect detection wafer graph optimization method, the prober data is imported into the machine end, the wafer prober map is generated, the wafer prober map is compared with the wafer map of the machine end, invalid chips can be marked efficiently and accurately, optimization of the wafer map is achieved, the capacity of the machine is released, time is saved, and manpower consumption is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor defect detection, in particular to a defect detection wafer map optimization method and an optimization system thereof. Background technique [0002] During the defect detection process, it was found that the wafer edge defect count (total amount of defects on the wafer edge) was relatively high, including defects (defects) caused by litho (lithography) defocus (out of focus) and CMP (chemical mechanical planarization) and TF ( Discolor (plastic package discoloration) and other defects caused by plastic package cutting), the number of such defects is relatively large, and some of them are located in chips that do not need needle testing in the future (that is, invalid chips, which are of low value and are usually discarded), which will cause Other key defects (defects on effective chips) are submerged in it and cannot be effectively alarmed, and subsequent defect detection sites can be caugh...

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Problems solved by technology

[0002] During the defect detection process, it was found that the wafer edge defect count (total amount of defects on the wafer edge) was relatively high, including defects (defects) caused by litho (lithography) defocus (out of focus) and CMP (chemical mechanical planarization) and TF ( Discolor (plastic package discoloration) and other defects caused by plastic package cutting), the number of such defects is relatively large, and some of them are located in chips that do not need needle testing in the future (that is, invalid chips, which are of low value and are usually discarded), which will cause Other key defects (defects on effective chips) are submerged in it and cannot be effectively alarmed, and subsequent defect detection sites can be caught (detected), which will affect the monitor of multiple processes (procedures).

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