FEMFET device and method for producing same

Abstract

The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.

Description

technical field [0001] The invention relates to a ferroelectric memory field effect transistor device (hereinafter referred to as FEMFET) and a manufacturing method thereof. Background technique [0002] The device has: a semiconductor substrate; at least one field effect transistor disposed on the semiconductor substrate and having a source region, a drain region, a channel region and a gate stack (gate stack); The stack has at least one ferroelectric layer; the gate stack (GS) has at least one thin diffusion barrier layer (50), which is arranged on the bottom of the ferroelectric layer (FE) and the semiconductor substrate (10 ) and its configuration structure should basically prevent the components of the ferroelectric layer (or layer) (FE) from diffusing to the semiconductor substrate (10); at least one dielectric buffer layer (60) is arranged on the ferroelectric layer ( FE) and the semiconductor substrate (10) on the gate stack (GS); and the diffusion barrier layer (50...

AI Technical Summary

Problems solved by technology

[0011] The diffusion process between the ferroelectric material and the components such as the semiconductor substrate will have an adverse effect on the characteristics of the transistor, which is the deficiency of the above-mentioned known solutions

Although this problem can be overcome by increasing the dielectric buffer layer d, the above problems will inevitably increase the risk of electrical breakdown

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