Generation method, device, computer equipment and storage medium of verification platform
A verification platform and computer program technology, applied in computing, instrumentation, error detection/correction, etc., can solve problems such as low efficiency of verification platform construction, and achieve the effect of improving construction efficiency
Active Publication Date: 2021-11-12
北京欣博电子科技有限公司
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[0003] However, when the verification platform of the chip is not in the UVM environment, the original VIP needs to be disassembled and reorganized to form a new verification platform suitable for the new operating environment, resulting in low efficiency in building the verification platform
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[0051] In one embodiment, it is an implementable manner before step S200, including:
[0052] Delete the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; wherein, the basic package represents the general library corresponding to the first operating environment, and the error reporting mechanism is used to report an error when the verification model is called greater than 0.
[0053] Specifically, the error reporting mechanism refers to a mechanism for reporting an error when the time when the verification model is called is greater than 0. Specific to the first operating environment, it can be judged based on whether the startup time of the verification model VIP in the basic package is 0 o’clock, and through the preset character matching, in the basic package, the search is based on the first operating environment and the verification model VIP is checked. The mechanism of starting the limit at 0 point...
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The present application relates to a method, device, computer equipment and storage medium for generating a verification platform. The method includes: obtaining a verification model suitable for the first operating environment; adding a calling interface at the initial calling position of the verification model to obtain a target verification model; instantiating the calling interface in the target verification platform; wherein, the target verification platform is applicable The verification platform of the second operating environment; calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform. Therefore, by adding a call interface to the verification model corresponding to the first operating environment, the obtained target verification model can be called by the verification platform of the second operating environment, so as to achieve the whole package integration of the verification model corresponding to the first operating environment into the second In the verification platform corresponding to the second operating environment, the construction efficiency of the verification platform has been improved.
Description
technical field [0001] The present application relates to the technical field of chip testing, in particular to a method, device, computer equipment and storage medium for generating a verification platform. Background technique [0002] With the development of chip manufacturing technology, a system-level verification technology for chip performance has emerged, and the performance and logic of the chip can be verified through test cases. In the test and verification of chips, the traditional technology is generally based on Universal Verification Methodology (Universal Verification Methodology, UVM), write a verification model (Verification IP, VIP) for testing, and then integrate a certain number of VIPs into the UVM environment. In the verification platform, the chip is verified through the UVM verification platform. [0003] However, when the verification platform of the chip is not in the UVM environment, the original VIP needs to be disassembled and reorganized to fo...
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IPC IPC(8): G06F11/36
CPCG06F11/3664G06F11/3688G06F11/3696
Inventor 金傲寒梁敏学
Owner 北京欣博电子科技有限公司