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Iteration method and device for accumulation calculation of interlayer coupling part of large-scale integrated circuit

A technology of large-scale integrated circuits and integrated circuits, applied in CAD circuit design, complex mathematical operations, design optimization/simulation, etc., can solve the problems of increasing the number of non-zero elements of sparse matrices, the complexity of solving sparse matrices, and long calculation time

Active Publication Date: 2021-06-18
北京智芯仿真科技有限公司
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  • Application Information

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Problems solved by technology

Since the method of moments only integrates for the interface, it will reduce a large number of grid units and unknown quantities. However, since the scale of integrated circuits ranges from nanometers to centimeters, directly solving the whole integrated circuit with the finite element method itself will cause problems. Huge sparse matrix, and due to the coupling of the finite element method and the method of moments, the formed coupling matrix is ​​a dense matrix at the interface, which greatly increases the number of non-zero elements of the entire sparse matrix and the complexity of the sparse matrix solution, making the calculation time still very long

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  • Iteration method and device for accumulation calculation of interlayer coupling part of large-scale integrated circuit
  • Iteration method and device for accumulation calculation of interlayer coupling part of large-scale integrated circuit
  • Iteration method and device for accumulation calculation of interlayer coupling part of large-scale integrated circuit

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[0041] In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below in conjunction with the drawings in the embodiments of the present invention.

[0042] It should be noted that: in the drawings, the same or similar symbols represent the same or similar elements or elements with the same or similar functions. The described embodiments are part of the embodiments of the present invention, but not all of the embodiments. In the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0043] In describing the present invention, it is to be understood that...

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Abstract

The invention provides an iteration method and device for accumulation calculation of a coupling part between layers of a large-scale integrated circuit, and the iteration method comprises the following steps: firstly, setting the initial values of the active layers of all source layers as all layers of the integrated circuit, secondly, carrying out the circulation of the mth source layer, and if the accumulation influence of other layers on the mth source layer Gm is greater than 0, using the influence Gm as a right end item to update the electromagnetic field and current distribution of the mth layer, and obtaining the variation of the field of the layer; based on the newest current distribution of the mth source layer, calculating the influence Gml of the mth source layer on all the action layers l of the mth source layer, and accumulating the influence to the influence G1 of the l layer; then, layers which can be ignored being determined through an effective influence value of a dynamically-calculated vector Green function, and then the action layer range of the mth layer being modified; and iterating the source layer repeatedly until the variation of all fields is smaller than a specified threshold, and ending the iteration. According to the method, the complexity and occupied memory of large-scale integrated circuit simulation can be remarkably reduced under the condition that the calculation precision is not reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an iterative method and device for accumulative calculation of coupling parts between layers of large-scale integrated circuits. Background technique [0002] When the integrated circuit is working, due to the transmission of high-speed signals on its multi-layer layout, a high-frequency alternating electromagnetic field will be formed. on a small semiconductor substrate. In order to achieve more functions, VLSI has dozens to hundreds of layers of structure, each layer structure is extremely complex, integrating millions or even tens of millions of transistors, and has a multi-scale structure, from the centimeter level to the latest state-of-the-art nanoscale. In order to ensure that the integrated circuit can work normally and realize the functions designed in advance, it is necessary to ensure the power integrity and signal integrity of the integrated circuit firs...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/23G06F30/33G06F17/16G06F17/18
CPCG06F17/16G06F17/18G06F30/23G06F30/33
Inventor 唐章宏邹军汲亚飞王芬黄承清
Owner 北京智芯仿真科技有限公司