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Semiconductor structure and fabrication method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as inability to meet chip protection requirements, inability to protect chips, small interception area, etc., and achieve semiconductor The effect of stable structure, strong protection and large interception area

Active Publication Date: 2022-04-26
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the poor stability and small interception area of ​​the existing sealing ring, it cannot provide stronger protection for the chip and cannot meet the protection requirements of the chip.

Method used

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  • Semiconductor structure and fabrication method thereof
  • Semiconductor structure and fabrication method thereof
  • Semiconductor structure and fabrication method thereof

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Embodiment Construction

[0069] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. A preferred embodiment of the application is shown in the drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

[0071] It will be understood that when an element or layer is referred to as being "on," "adjac...

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Abstract

The present invention relates to a semiconductor structure and a manufacturing method thereof, comprising: a substrate, the substrate including a peripheral area and a chip area; a first dielectric layer located on the peripheral area and the chip area of ​​the substrate; A protective structure and a functional structure are respectively located in the first dielectric layer of the peripheral area and the chip area; wherein, the protective structure includes a first sub-section, a second sub-section and a third sub-section stacked in sequence , the functional structure includes a fourth sub-section and a fifth sub-section stacked in sequence, the total height of the first sub-section, the second sub-section and the third sub-section is the same as that of the fourth sub-section and the The overall height of the fifth subsection is the same. The semiconductor structure is more stable, the interception area is larger, and the protection effect on the chip is stronger.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] When the wafer is cut, the cutting method of the dicing line will generate a certain mechanical stress on the front and back of the wafer, which may cause chipping at the edge of the chip. The chipping problem will reduce the mechanical strength of the chip, and the cracks at the edge of the chip at the beginning will spread further in the subsequent packaging process or in the use of the chip product, which is likely to cause the chip to break and lead to the failure of the electrical performance of the chip. In order to protect the internal circuit of the chip, prevent dicing damage, and improve chip reliability, a semiconductor structure such as a sealing ring (Seal Ring) is usually designed around the chip. Moreover, the sealing ring structure also has th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/00H01L21/78
CPCH01L23/562H01L21/78
Inventor 杨年旺王蒙蒙
Owner CHANGXIN MEMORY TECH INC
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