Power semiconductor packaging structure
A power semiconductor and packaging structure technology, applied in the direction of output power conversion devices, electrical components, etc., can solve the problems of increasing power chips and clamping capacitor circuits, increasing power chip voltage spikes, electromagnetic interference, etc., to reduce risks and avoid Increase and decrease the effect of voltage spikes
Active Publication Date: 2021-07-02
苏州悉智科技有限公司
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Problems solved by technology
Due to the existence of parasitic inductance, it is easy to make the loop form electromagnetic interference, increase the voltage spike of the power chip during switching and passing, and also increase the loop between the power chip and the clamp capacitor
Method used
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[0018] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0019] The terms "including" and "having" and any variations thereof in the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device...
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A power semiconductor packaging structure comprises a substrate, a first semiconductor power chip module, a second semiconductor power chip module and a clamping capacitor, wherein the first semiconductor power chip module, the second semiconductor power chip module and the clamping capacitor are connected to the substrate through connecting materials and form a loop. The first semiconductor power chip module comprises a first power chip, the substrate is provided with a power supply grounding end and a communication grounding end, and a source electrode of the first power chip is respectively connected with the power supply grounding end and the communication grounding end. The source electrode of the first power chip is directly connected with the communication ground on the substrate, so that the increase of multiple loops is avoided; meanwhile, due to the reduction of the source electrode loop of the first power chip, the risk of electromagnetic interference of the circuit is effectively reduced, and the voltage peak of the first power chip in the switching-on and switching-off processes is reduced.
Description
【Technical field】 [0001] The invention relates to a power semiconductor packaging structure. 【Background technique】 [0002] For the basic half-bridge circuit composed of two power chips and clamping capacitors, the power chip is generally directly connected to the substrate through parasitic inductance. Due to the existence of parasitic inductance, it is easy to make the loop form electromagnetic interference, increase the voltage spike of the power chip during switching and passing, and also increase the loop between the power chip and the clamp capacitor. [0003] Therefore, it is necessary to improve the prior art to overcome the defects in the prior art. 【Content of invention】 [0004] The purpose of the present invention is to provide a power semiconductor packaging structure, which can reduce the loop formed between the power chip and the clamp capacitor, and can reduce the peak of the power chip during the turn-on and turn-off process. [0005] The object of the ...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H02M1/44H02M1/00
CPCH02M1/00H02M1/44
Inventor 蔡超峰
Owner 苏州悉智科技有限公司