Fabrication method of semiconductor structure
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of inability to form opening patterns, incomplete selective etching of target film layers, etc., and achieve the effect of ensuring effective progress
Active Publication Date: 2022-06-24
CHANGXIN MEMORY TECH INC
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Problems solved by technology
[0003] However, the etching of the area to be etched may be affected by adjacent areas, for example, a specific material is covered and cannot be exposed to the etchant, resulting in the failure to form the preset opening pattern, resulting in the selective etching of the target film layer. eclipse is not complete
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[0012] Figure 1 to Figure 18 It is a schematic structural diagram corresponding to each step of a method for fabricating a semiconductor structure. The fabrication method of the semiconductor structure includes the following steps:
[0013] refer to figure 1 , providing a substrate 11, the substrate 11 includes a first area 111, a second area 112 and a third area 113, the second area 112 is located between the first area 111 and the third area 113; on the substrate 11, sequentially stacked target layers are formed 121 , the protective layer 13 , the initial mask layer 141 and the initial intermediate layer 15 .
[0014] refer to figure 2 , a first photoresist layer 161 is formed on the initial intermediate layer 15, and the first photoresist layer 161 has a first opening pattern; the initial intermediate layer 15 is etched using the first opening pattern to form a middle groove 15a, and the middle groove 15a exposes the surface of the initial mask layer 141 .
[0015] T...
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An embodiment of the present invention provides a method for fabricating a semiconductor structure, including: sequentially forming a target layer, a first mask layer, an isolation layer, and an intermediate layer on a substrate, and having at least one first recess in the intermediate layer on the first region. A groove, having at least one second groove in the middle layer of the second zone; forming a filling layer, the filling layer fills the first groove and the second groove, and the upper surface of the filling layer is higher than the upper surface of the middle layer, The height difference between the top surface of the filling layer on the first region and the top surface of the filling layer on the second region is less than or equal to a first preset value; performing a maskless dry etching process to remove the part on the first region Filling the layer until the top surface of the sacrificial layer is exposed; removing the sacrificial layer covering the sidewall of the first groove to form a first opening in the first region; etching part of the target layer by using the first opening, and the remaining target layer constitutes the target pattern. The embodiment of the present invention is beneficial to completely etch the target layer to form the desired target pattern.
Description
technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular, to a method for fabricating a semiconductor structure. Background technique [0002] Before the selective etching of the film layer, it is generally necessary to form a mask layer with an opening pattern. The mask layer can be either a photoresist layer or a mask composed of one or more other materials. The opening pattern can be formed by exposure and development of photoresist, or by etching specific materials in the mixed material film layer. These specific materials are generally formed in specific positions in advance and occupy the positions of the opening patterns to be formed. [0003] However, the etching of the to-be-etched area may be affected by the adjacent areas. For example, certain materials are covered and cannot be exposed to the etchant, so that the predetermined opening pattern cannot be formed, thereby causing selective etching of the tar...
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IPC IPC(8): H01L21/308
CPCH01L21/3086
Inventor 郭帅
Owner CHANGXIN MEMORY TECH INC