Manufacturing method of semiconductor structure
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as inability to form opening patterns, incomplete selective etching of target film layers, etc.
Active Publication Date: 2021-07-06
CHANGXIN MEMORY TECH INC
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Problems solved by technology
[0003] However, the etching of the area to be etched may be affected by adjacent areas, for example, a specific material is covered and cannot be exposed to the etchant, resulting in the failure to form the preset opening pattern, resulting in the selective etching of the target film layer. eclipse is not complete
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[0012] Figure 1 to Figure 18 It is a structural schematic diagram corresponding to each step of a manufacturing method of a semiconductor structure. A method for fabricating a semiconductor structure includes the following steps:
[0013] refer to figure 1 , providing a substrate 11, the substrate 11 includes a first region 111, a second region 112 and a third region 113, the second region 112 is located between the first region 111 and the third region 113; on the substrate 11, target layers stacked in sequence are formed 121 , protective layer 13 , initial mask layer 141 and initial intermediate layer 15 .
[0014] refer to figure 2 , form a first photoresist layer 161 on the initial intermediate layer 15, the first photoresist layer 161 has a first opening pattern; utilize the first opening pattern to etch the initial intermediate layer 15 to form an intermediate groove 15a, an intermediate groove 15a exposes the surface of the initial mask layer 141 .
[0015] Where...
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The embodiment of the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps: sequentially forming a target layer, a first mask layer, an isolation layer and an intermediate layer on a substrate, forming at least one first groove in the intermediate layer on a first region, and forming at least one second groove in the intermediate layer on a second region; forming a filling layer, filling the first groove and the second groove with the filling layer, the upper surface of the filling layer being higher than the upper surface of the middle layer, and the height difference between the top surface of the filling layer located on the first area and the top surface of the filling layer located on the second area being smaller than or equal to a first preset value; performing a maskless dry etching process to remove a part of the filling layer on the first region until the top surface of the sacrificial layer is exposed; removing the sacrificial layer covering the side wall of the first groove to form a first opening in the first region; and etching a part of the target layer by using the first opening, wherein the remaining target layer forms a target pattern. According to the embodiment of the invention, the target layer can be completely etched, and the required target pattern can be formed.
Description
technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure. Background technique [0002] Before the selective etching of the film layer, it is generally necessary to form a mask layer with an opening pattern. The mask layer can be a photoresist layer or a mask composed of one or more other materials. The opening pattern can be formed by exposure and development of photoresist, or by etching specific materials in the mixed material film layer. These specific materials are generally formed in a specific position in advance to occupy the position of the opening pattern to be formed. [0003] However, the etching of the area to be etched may be affected by the adjacent area, for example, a specific material is covered and cannot be exposed to the etchant, resulting in the failure to form the preset opening pattern, resulting in the selective etching of the target film...
Claims
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IPC IPC(8): H01L21/308
CPCH01L21/3086
Inventor 郭帅
Owner CHANGXIN MEMORY TECH INC