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Fabrication method of semiconductor structure

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as abnormal target pattern morphology, achieve high density, avoid collapse, and reduce damage.

Active Publication Date: 2022-06-24
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the actual process, when the target pattern is obtained by using the dry etching process and the wet etching process, due to the problem of the etching selectivity ratio of different materials, the morphology of the finally obtained target pattern is often abnormal.

Method used

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  • Fabrication method of semiconductor structure
  • Fabrication method of semiconductor structure
  • Fabrication method of semiconductor structure

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Embodiment Construction

[0025] refer to figure 1 , providing a substrate 10, a first dielectric material layer 11a, a first sacrificial material layer 12 and a photoresist layer 13 stacked in sequence, and the photoresist layer 13 has an opening pattern.

[0026] The first sacrificial material layer 12 is a multi-layer structure, and specifically, includes a first sacrificial sub-layer 121 and a second sacrificial sub-layer 122 arranged in layers, and the first sacrificial sub-layer 121 is located on the first dielectric material layer 11a and the second sacrificial sub-layer 11a. Between the layers 122, the material of the second sacrificial sub-layer 122 is the same as the material of the first dielectric material layer 11a.

[0027] refer to figure 2 , with photoresist layer 13 (reference figure 1 ) as a mask, etching to remove part of the first sacrificial material layer 12 (refer to figure 1 ), the first sacrificial material layer 12 remains as the first sacrificial layer 12a, and the fir...

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PUM

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Abstract

An embodiment of the present invention provides a method for fabricating a semiconductor structure, including: providing a substrate; forming an insulating layer on the substrate, the insulating layer including a first dielectric layer and a second dielectric layer; wherein the insulating layer has a first groove, The second dielectric layer covers the upper surface of the first dielectric layer; forming a protective layer, the protective layer covers the upper surface of the second dielectric layer, the bottom and the sidewall of the first trench; removing part of the protective layer to expose the second dielectric layer At least part of the surface; using a first wet etching process to remove the second dielectric layer, the first wet etching process has a first etching selectivity ratio for the material of the second dielectric layer and the material of the first dielectric layer; using the second The protective layer is removed by a wet etching process, and the second wet etching process has a second etching selectivity ratio between the material of the protective layer and the material of the first dielectric layer, and the second etching selectivity ratio is greater than the first etching selectivity ratio. The embodiments of the present invention are beneficial to optimize the morphology of the finally formed target pattern.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular, to a method for fabricating a semiconductor structure. Background technique [0002] In the fabrication process of the semiconductor structure, the dry etching process and the wet etching process can be selected according to actual needs. The dry etching process mainly uses reactive gas and plasma etching to remove materials in a specific area. The wet etching process It mainly uses chemical reagents to react with the material to be etched to remove specific exposed materials. Compared with the dry etching process, the wet etching process has a higher etching selectivity ratio. In the actual process, when the target pattern is obtained by the dry etching process and the wet etching process, due to the problem of the etching selectivity ratio of different materials, the morphology of the final obtained target pattern is often abnormal. How to solve the above ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311
CPCH01L21/31111H01L21/31144
Inventor 宛强夏军占康澍李森徐朋辉刘涛
Owner CHANGXIN MEMORY TECH INC