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Semiconductor device and array layout thereof and package structure comprising the same

A technology of semiconductor and isolation structure, applied in the field of three-dimensional semiconductor device and its array layout and packaging structure including it, capable of solving problems such as leakage current and excessive erasure of non-volatile memory

Pending Publication Date: 2021-07-09
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, non-volatile memory (such as flash memory) may have the problem of overerase due to low threshold voltage, resulting in leakage current

Method used

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  • Semiconductor device and array layout thereof and package structure comprising the same
  • Semiconductor device and array layout thereof and package structure comprising the same
  • Semiconductor device and array layout thereof and package structure comprising the same

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Embodiment Construction

[0086] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0087] Figure 1A to Figure 8B A schematic diagram illustrating a manufacturing process of the semiconductor device 100 according to an embodiment of the present invention is shown. Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A Draw the plane formed by the X-axis and the Y-axis, Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B Show the plane formed by the X-axis and the Z-axis.

[0088] Figure 1A A top view after forming the opening 108 is shown. Figure 1B drawn along Figure 1A The cross-sectional view of the line A-A' of , that is, the corresponding area 10 of one of the memory strings is s...

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Abstract

A semiconductor device and an array layout thereof and a package structure comprising the same are disclosed. The semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first location and a second location of the channel layer. The first location is opposite to the second location. The first location is surrounded by the memory structure, and the second location is exposed from the memory structure.

Description

technical field [0001] The present invention relates to a semiconductor device and its array layout and its packaging structure, and in particular to a three-dimensional semiconductor device and its array layout and its packaging structure. Background technique [0002] Recently, nonvolatile memory has been in increasing demand due to its advantage that stored data does not disappear when the current is turned off. [0003] However, non-volatile memory (such as flash memory) may cause overerase due to a low threshold voltage, resulting in leakage current. Therefore, there is still an urgent need to develop an improved non-volatile memory to solve the above problems. Contents of the invention [0004] The present invention relates to a semiconductor device, wherein the channel layer has a first location and a second location opposite, since the memory structure surrounds the first location and exposes the second location, compared to both the first location and the second ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11565H01L27/1157H01L27/11582H01L27/11587H01L27/1159H01L27/11597H01L29/06
CPCH01L29/0638H01L29/0649H10B43/10H10B43/35H10B51/10H10B51/20H10B51/30H10B43/27H01L29/40117H01L29/40111H10B43/20H01L29/42344H10B43/30
Inventor 吕函庭
Owner MACRONIX INT CO LTD
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