Manufacturing method of 3D memory device

Abstract

The present application discloses a 3D memory device and a manufacturing method thereof. The 3D memory device includes: a gate stack structure located above a substrate, including a plurality of gate conductors and a plurality of interlayer insulating layers stacked alternately; a plurality of channel pillars and a plurality of dummy channel pillars, penetrating the gate A laminated structure; a first adhesive layer is located on the sidewall of the dummy channel hole, and is located between a plurality of the interlayer insulating layers, and is adjacent to a plurality of the gate conductors; a core part is located at the Inside the dummy channel hole, the sidewall and bottom of the dummy channel hole are filled, and the first adhesion layer is an oxide formed by oxidizing nitride. A first adhesion layer is formed by oxidizing nitride into oxide on the sidewall of the dummy channel hole, and a plurality of interlayer insulating layers and cores are bonded to form a support frame in the gate stack structure, ensuring that the stack structure support to prevent the influence of subsequent high temperature processes.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and methods of manufacturing the same. Background technique [0002] The development direction of semiconductor technology is the reduction of feature size and the improvement of integration. For memory devices, the improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature sizes of semiconductor manufacturing processes are getting smaller and smaller, the storage density of memory devices is getting higher and higher. In order to further increase the storage density, three-dimensionally structured memory devices (ie, 3D memory devices) have been developed. 3D memory devices include multiple memory cells stacked in a vertical direction, which can exponentially increase the level of integration on a wafer per unit area, and can reduce costs. In 3D memory devices, gat...

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Problems solved by technology

[0003] With the increase in the number of layers of the gate stack structure of 3D memory, the difficulty of etching increases, and the requirements for the support of the dummy channel pillars are higher, and the corresponding filling process also has different requirements. At present, for example, furnace tube oxidation is used. process or oxide filling process to manufacture false channel pillars, but these processes have various shortcomings due to technical limitations. The process of filling false channel pillars with furnace tube oxidation process is long and the film thickness consistency is poor. It is also necessary to remove the deposits on the back of the wafer, which is time-consuming and laborious, and may also cause problems such as depressions and deformations on the top of the false channel pillars, which will further affect the reliability of the memory device

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