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Driving d-mode fets in half-bridge driver configuration

A technology of driver and driving voltage, which is used in semiconductor devices, output power conversion devices, logic circuit connection/interface layout, etc.

Pending Publication Date: 2021-07-23
PSEMI CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] In view of what was described in the previous sections, the methods and apparatus taught in this disclosure turn off and turn on D-type FETs in a half-bridge architecture by providing negative and non-negative voltages between their gate-sources, respectively. , which solves the problem of driving D-type FETs in half-bridge architectures

Method used

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  • Driving d-mode fets in half-bridge driver configuration
  • Driving d-mode fets in half-bridge driver configuration
  • Driving d-mode fets in half-bridge driver configuration

Examples

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Embodiment approach

[0044] refer to Figure 3A , the drivers (DRV1, DRV2) may receive their respective drive input signals from the driver inputs (in1, in2). According to an embodiment of the present disclosure, the driver input signal may be a non-overlapping square wave signal to ultimately ensure that the high-side FET (T2) and the low-side FET (T1) are not turned on at the same time, which would cause possible damage to the circuit current spikes (thru).

[0045] further reference Figure 3A , the tail resistor (R) will determine the high-side capacitor (C HS ) will be charged at a rate. Embodiments according to the present disclosure are conceivable in which the resistor (R) is a variable resistor. According to other embodiments of the present disclosure, the resistor (R ). In some applications, such adjustments may not be desired. In the following, other embodiments according to the present disclosure that handle such applications are described.

[0046] Figure 2C An exemplary cha...

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Abstract

Methods and devices to drive D-mode and E-mode power FETs are described. The disclosure teaches how to apply negative voltages across gate-source of D-mode FETs to turn such FETs off whenever needed. The presented method and devices can also be used in applications where overdriving D-mode FETs to achieve improved on resistance is desired.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Patent Application Serial No. 16 / 186,323, filed November 9, 2018, entitled "Driving D-Mode FETS In Half-Bridge Driver Configuration," which is incorporated by reference in its entirety into this article. [0003] This application may be related to US Patent No. 9,484,897 B2, issued November 1, 2016, entitled "Level Shifter," which is incorporated herein by reference in its entirety. [0004] background technical field [0005] The present disclosure relates to half bridge drivers, and more particularly to methods and apparatus for driving both depletion mode (D-mode) field effect transistors (FETs) and enhancement mode E-mode field effect transistors (FETs) using a single circuit architecture . Background technique [0006] Certain D-type FETs are good candidates for high-efficiency half-bridge architectures due to their improved electrical characteristics such as high mobili...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/12H03K17/687
CPCH03K2017/6875H03K17/063H03K2217/0081H02M3/158H03K7/08H03K17/223H03K17/687H03K19/0185H03K19/09443H03K2017/066
Inventor 阿雷祖·巴盖里布迪卡·阿贝辛哈
Owner PSEMI CORP