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Three-dimensional memory and preparation method thereof

A memory, three-dimensional technology, applied in semiconductor devices, electric solid-state devices, electrical components, etc., can solve problems such as affecting the electrical performance of three-dimensional memory, abnormal function of top selection transistors, etc., to improve stability, reliability, and process complexity. low effect

Active Publication Date: 2021-08-03
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In other words, the threshold voltage Vt of the top selection transistor will drift, so that the function of the top selection transistor is abnormal or invalid, thereby affecting the electrical performance of the three-dimensional memory

Method used

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  • Three-dimensional memory and preparation method thereof
  • Three-dimensional memory and preparation method thereof
  • Three-dimensional memory and preparation method thereof

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Embodiment Construction

[0025] For a better understanding of the application, various aspects of the application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are descriptions of exemplary embodiments of the application only, and are not intended to limit the scope of the application in any way.

[0026] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms "comprises", "includes", "includes" and / or "includes" indicate the presence of said features, integers, elements, components and / or combinations thereof, but do not exclude The presence of one or more other features, integers, elements, components and / or combinations thereof.

[0027] The description herein is made with reference to schematic illustrations of exemplary embodiments. Exemplary embodiments disclosed herein should not be constru...

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Abstract

The invention provides a three-dimensional memory and a preparation method thereof. The method comprises the following steps: forming a laminated structure comprising dielectric layers and sacrificial layers which are alternately laminated on a substrate; forming a channel hole penetrating through the laminated structure, and sequentially forming a functional layer and a channel layer on the side wall of the channel hole to form a channel structure; forming a top selection gate cut penetrating through the at least one sacrificial layer; sequentially removing the at least one sacrificial layer and a part, corresponding to the at least one sacrificial layer, of the functional layer through the top selection gate notch to form a selection gate gap; and forming an insulating layer on the inner wall of the selection gate gap, and forming a selection gate layer in the selection gate gap where the insulating layer is formed. According to the three-dimensional memory and the preparation method thereof, the stability of the threshold voltage of the top selection transistor can be improved, and the reliability of the top selection transistor is improved.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and more specifically, to a three-dimensional storage device and a manufacturing method thereof. Background technique [0002] As NAND flash technology advances, 3D NAND architectures can scale to higher storage densities without sacrificing data integrity, enabling greater storage capacity. [0003] In a 3D NAND memory, a memory array is usually formed by a channel structure, and the channel structure includes a plurality of memory cells in a vertical direction, thereby forming memory cells (cells) arranged in an array in a three-dimensional direction. Both ends of each channel structure can be respectively connected to a bit line (BL) and a common source line (CSL), so that the channel structure can form a circuit loop. In addition, the top of the channel structure includes one or more top selection transistors, and the switching on or off of the circuit in the channel structu...

Claims

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Application Information

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IPC IPC(8): H01L27/1157H01L27/11582
CPCH10B43/35H10B43/27H10B41/27H10B41/10H10B43/10
Inventor 杨远程刘磊周文犀
Owner YANGTZE MEMORY TECH CO LTD