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Semiconductor packages and methods of manufacturing thereof

A technology for semiconductors and semiconductor tubes, applied in the field of semiconductor packaging and its manufacturing, can solve the problems of reducing overall efficiency, increasing the cost of die, and difficult to support thin semiconductor die.

Pending Publication Date: 2021-08-13
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] However, the can / lid approach requires a relatively large gate pad size, which reduces the active area of ​​the power semiconductor device, and thus increases die cost and reduces overall efficiency
Additionally, can / lid solutions do not readily support thin semiconductor die (e.g., 40 μm to 60 μm thick or thinner) due to bond wire thickness issues that can arise when thermal material climbs up the sidewalls of a thin power semiconductor die
Excessive creepage can cause electrical problems, which are unavoidable with thin semiconductor die

Method used

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  • Semiconductor packages and methods of manufacturing thereof
  • Semiconductor packages and methods of manufacturing thereof
  • Semiconductor packages and methods of manufacturing thereof

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0122] Example 1. A semiconductor package comprising: an insulating substrate having a first main side and a second main side opposite the first main side; a power semiconductor die embedded in the insulating substrate and compared The insulating substrate is thin or as thick as the insulating substrate, the power semiconductor die comprising a first load terminal on a first side facing in the same direction as the first main side of the insulating substrate Bonding pads, second load terminal bonding pads at the second side facing the same direction as the second main side of the insulating substrate, and control terminal bonding pads at the first side or the second side Plate; Conductive first via, which extends through the insulating substrate in a peripheral region laterally surrounding the power semiconductor die; first metallization, which connects the power semiconductor die at the first main side of the insulating substrate A first load terminal bonding pad connected to...

example 2

[0123] Example 2. The semiconductor package of example 1, wherein the control terminal bond pad is at the second side of the power semiconductor die, the semiconductor package further comprising: a solderable third contact pad, It is at the second main side of the insulating substrate and is formed by control terminal bond pads of the power semiconductor die.

example 3

[0124] Example 3. The semiconductor package of example 1, wherein the control terminal bond pad is at the first side of the power semiconductor die, the semiconductor package further comprising: a conductive second via at extending through the insulating substrate in the peripheral region; a second metallization connecting a control terminal bond pad of the power semiconductor die to a second via at the first main side of the insulating substrate; and A solderable third contact pad at the second main side of the insulating substrate and formed by the second via.

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Abstract

Semiconductor packages described herein include a thermal capacitor designed to absorb transient heat pulses from a power semiconductor die and subsequently release the transient heat pulses to a surrounding environment, and / or a recessed pad feature. Corresponding methods of production are also described.

Description

Background technique [0001] Cooling capability is disadvantageous for SMD (Surface Mount Device) based power electronics. However, SMD based systems offer high efficiency and are therefore widely used. Some power SMD packaging solutions offer low thermal resistance to the top and bottom sides of the package and instead of using bond wires or clip interconnects, solder bumps are used for the source and gate connections. The drain connection is formed by a copper plated can (lid) bonded to the drain side of the power semiconductor die. The can / lid provides low thermal resistance to the top side of the package and is ideal for cooling through the top side of the package, providing a dual-sided cooling solution. [0002] However, the can / lid approach requires a relatively large gate pad size, which reduces the active area of ​​the power semiconductor device, and thus increases die cost and reduces overall efficiency. Additionally, the can / lid approach does not readily support t...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L23/31H01L23/13H01L23/367
CPCH01L21/486H01L23/3121H01L23/13H01L23/367H01L23/5389H01L23/427H01L2224/04105H01L2224/0603H01L2224/06181H01L2224/96H01L2224/2518H01L24/96H01L2924/19041H01L2224/32265H01L2924/19104H01L23/642H01L24/19H01L2924/13091H01L2924/13055H01L2224/24137H01L23/142H01L23/4827H01L23/49827
Inventor 赵应山T·纳耶夫P·帕尔姆
Owner INFINEON TECH AG
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