Ultra-low power consumption high-speed comparator circuit implementation method

Abstract

The invention discloses an ultra-low power consumption high-speed comparator circuit implementation method, which relates to the field of integrated circuits and comprises a comparator and a latch. The comparator comprises an input sampling amplification geminate transistor, a third NMOS (N-channel Metal Oxide Semiconductor) transistor, a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; the latch comprises a comparison pre-amplification geminate transistor, a fourth NMOS (N-channel Metal Oxide Semiconductor) transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS (P-channel Metal Oxide Semiconductor) transistor and a sixth PMOS transistor; in the sampling stage, the latch is in a reset state and has no power consumption; and in the holding stage, the latch does not have a power-to-ground access and does not consume power. The method is simple in design and easy to implement, has the characteristics of high speed and low power consumption, and can be ensured to be always in a linear amplification region by introducing a feedback system.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method for realizing an ultra-low power consumption high-speed comparator circuit. Background technique [0002] At this stage, the integration level of integrated circuits is getting higher and higher, and the module speed and power consumption requirements of chip integration are getting higher and higher. In particular, the quantization process from analog signal to digital signal and the performance index requirements of analog to digital quantization are getting higher and higher. Such as figure 1 As shown, it is a traditional comparator design. The disadvantage is that there will be a path from VDD to VSS during the sampling phase of the preamplifier (Preamp) and latch (Latch). Therefore, there will be a large current depending on the design. There will be great shortcomings in the application field of consumption. [0003] Therefore, those skilled in the art are dev...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, it is a traditional comparator design. The disadvantage is that there will be a VDD to VSS path in the sampling phase of the preamplifier (Preamp) and the latch (Latch). Therefore, there will be a large current depending on the design. Consumption application field will have great defects

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