Method for performing IC scan chain circuit test based on multiple FPGAs

Abstract

The invention relates to a method for performing IC scan chain circuit test based on multiple FPGAs. By adopting the idea of cascade expansion, the problem of insufficient storage resources when a single FPGA (Field Programmable Gate Array) is used as a storage entity of the SCAN (Spatial Clustering Area Network) CHAIN pattern is solved. Through self-defined communication handshake mode between FPGAs, a next-level FPGA can know that a previous-level FPGA has completed test and a current-level FPGA needs to be started to work, and after the current-level FPGA completes test, the next-level FPGA is notified to start working. According to the invention, a series chain working principle is adopted, and a huge SCAN CHAIN test vector test is realized.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a method for testing IC scan chain circuits based on multiple FPGAs. Background technique [0002] Inserting scan chain in chip design is one of the important methods of digital integrated circuit testing. This method can effectively screen out bad chips and improve product quality. For scan chain testing, the industry usually uses ATE equipment (aotuomatic test equipment) to test it. This equipment is highly specialized, expensive, and limited in usage scenarios, so it can only be used in professional IC testing factories; [0003] Later, a design house invented a scan chain test method based on the fpga platform, but this method is limited by the fpga resources of the selected fpga platform. For large-scale IC projects, scan chain incentives and comparison files It may be >XX giga bit. If the RAM and LUT resources of the fpga platform are insufficient, the test require...

AI Technical Summary

Problems solved by technology

For scan chain testing, the industry usually uses ATE equipment (aotuomatic test equipment) to test it. This equipment is highly specialized, expensive, and has limited use scenarios, so it can only be used in professional IC testing factories;

[0003] Later, a design house invented a scan chain test method based on the fpga platform, but this method is limited by the fpga resources of the selected fpga platform. For large-scale IC projects, scan chain incentives and comparison files It may be >XX giga bit. If the RAM and LUT resources of the fpga platform are insufficient, the test requirements for the scan chain circuit cannot be completed at one time. The test plan for the scan chain needs to be divided into many small plans to complete, which is time-consuming and labor-intensive. ,low efficiency

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