Circuit aging test method based on BIST structure and self-oscillation ring

Abstract

The invention discloses a circuit aging test method based on a BIST structure and a self-oscillation ring. The method comprises the following steps: 1, selecting a representative key path set according to static time sequence analysis, strong correlation and a fan-out filtering method; 2, analyzing a logic gate on each representative key path, replacing a first gate with a gate which is of the same type and is additionally provided with an input pin, connecting a bypass multi-selector on the added pin to connect the representative key paths into a loop, and determining a non-control pin value of each logic gate to configure the logic gate into a self-oscillation ring; 3, generating an aging test vector by using a fixed fault test vector generation method, and sensitizing a key path; 4, after sensitizing the key path, forbidding a system clock, setting oscillation time by using an off-chip timer, and simultaneously controlling a self-oscillation ring to start oscillation; and 5, designing an asynchronous counter based on a BIST structure, calculating circuit delay, and evaluating the aging degree of the circuit.

Description

technical field [0001] The invention relates to integrated circuit testing technology and reliability technology, especially in aging prediction and protection of ultra large scale integrated circuits. Background technique [0002] With the shrinking of the integrated circuit process size, the circuit performance and integration degree have been greatly improved. However, the long-term load operation of the chip in special environments such as high temperature and high pressure will reduce the performance of the chip, leading to increasingly serious aging problems of the chip, which may eventually lead to chip failure. Especially in the safety-critical fields, the rapid development of autonomous driving and satellite systems, the support of safe and reliable chip design is very important, and the problem of chip aging has become an increasingly challenging problem in integrated circuits. [0003] Under advanced process conditions, the aging problem faced by chips is becomin...

AI Technical Summary

Problems solved by technology

[0006] In order to overcome the problems of large hardware overhead and inaccurate testing in the existing aging test method, and the hardware structure affects the timing of the critical path, the present invention provides a circuit aging test method based on a BIST structure and a self-oscillating ring, in order to achieve a lower cost. The hardware overhead accurately tests the aging degree of the circuit without affecting the critical path timing and circuit performance, providing an accurate basis for evaluating circuit performance and service life, and improving the reliability of aging detection

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