Flat electric field groove semiconductor chip terminal structure and preparation method thereof
A terminal structure and semiconductor technology, applied in the direction of semiconductor devices, circuits, electrical components, etc., can solve the problems of surface fluctuation peak value, uneven distribution of electric field on the surface of terminal structure, etc.
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no. 1 example
[0068] figure 2 It is a schematic cross-sectional view of the flat electric field trench structure of the power semiconductor chip in this embodiment, as figure 2 As shown, it includes: N-type substrate 101 , P region 2 , P+ region 3 , oxide layer 4 , polysilicon field plate 5 , insulating layer 6 , metal field plate 7 , and passivation layer 8 .
[0069] image 3 It is a schematic diagram of the Y-axis logarithmic curve of the BV simulation of the conventional field-limiting ring terminal structure in this embodiment;
[0070] Figure 4 It is a schematic diagram of the Y-axis logarithmic curve of the flat electric field trench terminal structure BV simulation in this embodiment;
[0071] Figure 5 It is a schematic diagram of the electric field distribution of the conventional field-limiting ring terminal structure in this embodiment;
[0072] Figure 6 It is a schematic diagram of the electric field distribution of the flat electric field trench terminal structure in...
no. 2 example
[0105] Figure 9 It is a schematic flow chart of a method for preparing a flat electric field trench power semiconductor chip according to an example of the present invention;
[0106] Figure 10 It is a schematic cross-sectional view of a chip structure corresponding to steps S100 and S200 in an example of the present invention;
[0107] Figure 11 It is a schematic cross-sectional view of a chip structure corresponding to steps S300 and S400 in an example of the present invention;
[0108] Figure 12 It is a schematic cross-sectional view of a chip structure corresponding to step S500 in an example of the present invention;
[0109] Figure 13 It is a schematic cross-sectional view of a chip structure corresponding to steps S600 and S700 in an example of the present invention;
[0110] Figure 14 It is a schematic cross-sectional view of a chip structure corresponding to step S800 in an example of the present invention.
[0111] The schematic cross-sectional view of ...
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Abstract
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