Three-dimensional memory

A memory, three-dimensional technology, applied in the direction of electric solid-state devices, semiconductor devices, semiconductor/solid-state device components, etc., to achieve the effect of improving bonding reliability

Active Publication Date: 2021-09-24
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] The present application provides a three-dimensional memory that can at least partially solve the above-mentioned problems in the prior art, so as to solve the reliability problem in the bonding process of the contact structure between the array wafer and the peripheral wafer under the inverted X-tacking architecture

Method used

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Embodiment Construction

[0030] For a better understanding of the application, various aspects of the application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are descriptions of exemplary embodiments of the application only, and are not intended to limit the scope of the application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, expressions such as first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features, especially do not represent any sequential order. Thus, a first side discussed herein could also be termed a second side, and a first window could also be termed a second window, and vice versa, without departing from the teac...

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Abstract

One aspect of the present disclosure provides a three-dimensional memory including a peripheral wafer and an array wafer bonded to each other. The peripheral wafer includes peripheral circuitry for the array wafer. The array wafer comprises a to-be-tested structure which comprises a first test end and a second test end; a first test interconnection structure and a second test interconnection structure which are respectively connected to the first test end and the second test end; and a first pin connection structure and a second pin connection structure which are respectively connected to the first test end and the second test end of the to-be-tested structure through the first test interconnection structure and the second test interconnection structure.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, and in particular, relates to a three-dimensional memory with an X-tacking architecture. Background technique [0002] The three-dimensional memory with X-tacking architecture can effectively solve the problem that the peripheral circuit is affected by high temperature and high pressure when processing the memory array by arranging the memory array and peripheral circuits on separate array wafers and peripheral wafers, and can achieve higher Storage density, simpler process flow and reduced cycle times. [0003] In this architecture, when the two wafers are prepared, they can be bonded. As shown in FIG. 1 , the bonded array wafer 110 and the peripheral wafer 120 can pass through the array wafer contact parts respectively provided in the array wafer 110 (for example, the first array wafer contacts) at the bonding interface. part TVIA-1 to third array wafer contact part TVIA-3) an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L23/528H01L23/544
CPCH01L25/18H01L22/32H01L23/5283
Inventor 姚兰薛磊华子群胡思平尹朋岸严孟
Owner YANGTZE MEMORY TECH CO LTD
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