Model parameter test structure of transistor and preparation method thereof

A technology of model parameters and test structures, applied in the field of transistor manufacturing, can solve the problems of insufficient accuracy of electrical parameters of asymmetric transistors

Pending Publication Date: 2021-09-28
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Based on this, it is necessary to provide a transistor model parameter test structure and its preparation method for the problem of insufficient accuracy of the existing external test structure to extract the electrical parameters of the asymmetric transistor

Method used

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  • Model parameter test structure of transistor and preparation method thereof
  • Model parameter test structure of transistor and preparation method thereof
  • Model parameter test structure of transistor and preparation method thereof

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Embodiment Construction

[0058] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0060] In the...

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Abstract

The invention relates to a model parameter test structure of a transistor and a preparation method thereof, and the model parameter test structure comprises a substrate which is provided with a first conductive type, and is internally provided with a plurality of isolation structures, wherein the isolation structures are used for isolating different doped regions; a first test device which is formed in the substrate and used for acquiring characteristic parameters of the source side of the transistor, and a second test device which is formed in the substrate and used for acquiring characteristic parameters of the drain side of the transistor, wherein the first test device and the second test device are different in structure. For the transistor with an asymmetric structure, the first test device and the second test device are correspondingly prepared based on different device structures of the source electrode side and the drain electrode side, so that the model parameter extraction error caused by the test structure is reduced, and the extraction accuracy of the characteristic parameters of the source electrode side and the drain electrode side of the transistor is improved.

Description

technical field [0001] The invention relates to the technical field of transistor manufacturing, in particular to a model parameter test structure of a transistor and a preparation method thereof. Background technique [0002] With the continuous development of semiconductor technology, integrated circuits have grown from a few connected devices fabricated on a single chip to millions of devices, and the performance and complexity provided by current integrated circuits have also continued to increase. Various transistors, as the most basic devices in semiconductor manufacturing, are widely used in integrated circuits, so higher requirements are placed on the circuit design and manufacturing process of transistors. [0003] In order to accurately obtain the design and manufacturing conditions of the transistor, technicians usually extract the electrical parameters of the transistor, and use the extracted parameters to conduct simulations to confirm whether the transistor mee...

Claims

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Application Information

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IPC IPC(8): G01R31/26
CPCG01R31/2601H01L23/544H01L22/34G01R31/2607
Inventor 李国超
Owner CHANGXIN MEMORY TECH INC
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